diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:40 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:40 -0800 |
commit | ab2f864af2fd38cbf141708550409f3ca72c675f (patch) | |
tree | 75b861a290240275d872a58d393a6d6f7e5598d5 /tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | |
parent | ceae8383ffeebdc2c12d9a383941c62653471de1 (diff) | |
download | gem5-ab2f864af2fd38cbf141708550409f3ca72c675f.tar.xz |
m5: Regression Tester Update
This patch includes the necessary regression updates to test the new ruby
configuration system. The patch includes support for multiple ruby protocols
and adds the ruby random tester. The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses. These tests can be
added back in when ruby supports atomic mode for real.
--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 8a4afd8c9..c0deed77b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6560 # Simulator instruction rate (inst/s) -host_mem_usage 2303716 # Number of bytes of host memory used -host_seconds 0.89 # Real time elapsed on the host -host_tick_rate 26729951 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 24278 # Simulator instruction rate (inst/s) +host_mem_usage 347460 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 1220626 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23749000 # Number of ticks simulated +sim_seconds 0.000293 # Number of seconds simulated +sim_ticks 292960 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,7 +28,7 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 47498 # number of cpu cycles simulated +system.cpu.numCycles 292960 # number of cpu cycles simulated system.cpu.num_insts 5827 # Number of instructions executed system.cpu.num_refs 2090 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls |