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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-05-11 10:38:46 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-05-11 10:38:46 -0700 |
| commit | b174ec065e2b9f8ffa68c350b2563819eef5e9b1 (patch) | |
| tree | 247eaf664b887559a1575d0733daa2179741bcd2 /tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | |
| parent | 6df61e1f2409e336dc4ae68eaeae7d0638e65a9d (diff) | |
| download | gem5-b174ec065e2b9f8ffa68c350b2563819eef5e9b1.tar.xz | |
ruby: Initial references for ruby regressions
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..05c9c2369 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 10877 # Simulator instruction rate (inst/s) +host_mem_usage 201300 # Number of bytes of host memory used +host_seconds 0.52 # Real time elapsed on the host +host_tick_rate 44468411 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5656 # Number of instructions simulated +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 23131000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 46262 # number of cpu cycles simulated +system.cpu.num_insts 5656 # Number of instructions executed +system.cpu.num_refs 2055 # Number of memory references +system.cpu.workload.PROG:num_syscalls 13 # Number of system calls + +---------- End Simulation Statistics ---------- |