diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
| commit | 8833b4cd44457d50b45a4dfe642cdb5e51c0889d (patch) | |
| tree | 64417a9e2d759dc367848de4b7ee117b3903dc54 /tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | |
| parent | ec1a4cbbc73ecc1d7456d11c571c425e226a7d3b (diff) | |
| download | gem5-8833b4cd44457d50b45a4dfe642cdb5e51c0889d.tar.xz | |
Bus: Update the stats for the recent bus fix.
--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini')
| -rw-r--r-- | tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | 67 |
1 files changed, 66 insertions, 1 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 7da6cb048..1b246149f 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -11,7 +11,62 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache tlb toL2Bus tracer workload +CP0_Config=0 +CP0_Config1=0 +CP0_Config1_C2=false +CP0_Config1_CA=false +CP0_Config1_DA=0 +CP0_Config1_DL=0 +CP0_Config1_DS=0 +CP0_Config1_EP=false +CP0_Config1_FP=false +CP0_Config1_IA=0 +CP0_Config1_IL=0 +CP0_Config1_IS=0 +CP0_Config1_M=0 +CP0_Config1_MD=false +CP0_Config1_MMU=0 +CP0_Config1_PC=false +CP0_Config1_WR=false +CP0_Config2=0 +CP0_Config2_M=false +CP0_Config2_SA=0 +CP0_Config2_SL=0 +CP0_Config2_SS=0 +CP0_Config2_SU=0 +CP0_Config2_TA=0 +CP0_Config2_TL=0 +CP0_Config2_TS=0 +CP0_Config2_TU=0 +CP0_Config3=0 +CP0_Config3_DSPP=false +CP0_Config3_LPA=false +CP0_Config3_M=false +CP0_Config3_MT=false +CP0_Config3_SM=false +CP0_Config3_SP=false +CP0_Config3_TL=false +CP0_Config3_VEIC=false +CP0_Config3_VInt=false +CP0_Config_AR=0 +CP0_Config_AT=0 +CP0_Config_BE=0 +CP0_Config_MT=0 +CP0_Config_VI=0 +CP0_EBase_CPUNum=0 +CP0_IntCtl_IPPCI=0 +CP0_IntCtl_IPTI=0 +CP0_PRId=0 +CP0_PRId_CompanyID=0 +CP0_PRId_CompanyOptions=0 +CP0_PRId_ProcessorID=1 +CP0_PRId_Revision=0 +CP0_PerfCtr_M=false +CP0_PerfCtr_W=false +CP0_SrsCtl_HSS=0 +CP0_WatchHi_M=false +UnifiedTLB=true clock=500 cpu_id=0 defer_registration=false @@ -26,6 +81,7 @@ max_loads_any_thread=0 phase=0 progress_interval=0 system=system +tlb=system.cpu.tlb tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -69,6 +125,7 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=MipsDTB +size=64 [system.cpu.icache] type=BaseCache @@ -108,6 +165,7 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] type=MipsITB +size=64 [system.cpu.l2cache] type=BaseCache @@ -145,11 +203,16 @@ write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] mem_side=system.membus.port[1] +[system.cpu.tlb] +type=MipsUTB +size=64 + [system.cpu.toL2Bus] type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -167,6 +230,7 @@ euid=100 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 @@ -178,6 +242,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side |