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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-08 17:07:23 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-08 17:07:23 -0400 |
commit | 911381321b294fa5a8d2dd77eaabc7473ffe5e6f (patch) | |
tree | 538054637caf1ca613102be9ff4449508e624c99 /tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | |
parent | d3fba5aa30adfb006b99895e869ed175213d0134 (diff) | |
download | gem5-911381321b294fa5a8d2dd77eaabc7473ffe5e6f.tar.xz |
Update ref stats: ll/sc, cpu_id, new kernel (?)
--HG--
extra : convert_revision : 060cb7319c4474429917a6347a9a47f390208ec8
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini')
-rw-r--r-- | tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 040735f2c..af7a1c895 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -197,11 +199,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/mips/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -217,6 +225,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= |