Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558

1 files changed, 13 insertions, 0 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 040735f2c..8e1bb0388 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
@@ -64,6 +65,7 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 mem=system.cpu.dcache
+progress_interval=0
 system=system
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -192,20 +194,30 @@ mem_side=system.membus.port[1]
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
+egid=100
 env=
+euid=100
 executable=tests/test-progs/hello/bin/mips/linux/hello
+gid=100
 input=cin
 output=cout
+pid=100
+ppid=99
 system=system
+uid=100
 
 [system.membus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
@@ -217,6 +229,7 @@ port=system.membus.port[0]
 
 [trace]
 bufsize=0
+cycle=0
 dump_on_exit=false
 file=cout
 flags=