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| author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
| commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
| tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | |
| parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
| download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz | |
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini')
| -rw-r--r-- | tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index d6fb3e91a..ac73fcc0d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache tlb toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload CP0_Config=0 CP0_Config1=0 CP0_Config1_C2=false @@ -66,7 +66,6 @@ CP0_PerfCtr_M=false CP0_PerfCtr_W=false CP0_SrsCtl_HSS=0 CP0_WatchHi_M=false -UnifiedTLB=true checker=Null clock=500 cpu_id=0 @@ -85,7 +84,6 @@ numThreads=1 phase=0 progress_interval=0 system=system -tlb=system.cpu.tlb tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -124,7 +122,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] -type=MipsDTB +type=MipsTLB size=64 [system.cpu.icache] @@ -160,7 +158,7 @@ cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] -type=MipsITB +type=MipsTLB size=64 [system.cpu.l2cache] @@ -195,10 +193,6 @@ write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] mem_side=system.membus.port[1] -[system.cpu.tlb] -type=MipsUTB -size=64 - [system.cpu.toL2Bus] type=Bus block_size=64 |