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authorGabe Black <gblack@eecs.umich.edu>2006-10-09 19:55:49 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-09 19:55:49 -0400
commit5448517da4cd13e3c8438850f04367d9614d686b (patch)
tree14937f6dac2fd880e193d8bb6822703cae73cb99 /tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
parent843888c489c3337a041098a94fc2105359a74a9a (diff)
downloadgem5-5448517da4cd13e3c8438850f04367d9614d686b.tar.xz
updated reference output
--HG-- extra : convert_revision : daf11630290c7a84d63bf37cafa44210861c4bf2
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini')
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini4
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index af7a1c895..8e1bb0388 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -194,6 +194,8 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
@@ -214,6 +216,8 @@ uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]