diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2009-12-31 15:30:51 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2009-12-31 15:30:51 -0500 |
commit | 47a1f113811173ebd52365bbe09ec2477c003780 (patch) | |
tree | 1cf5e7040b8757c455ebe5a79c248c63f2ee1dfe /tests/quick/00.hello/ref/mips/linux/simple-timing | |
parent | 18dc80e07b4a4a6311c87bceee6a2154a4bb006e (diff) | |
download | gem5-47a1f113811173ebd52365bbe09ec2477c003780.tar.xz |
MIPS: Update stats for updated initial environment.
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing')
3 files changed, 118 insertions, 121 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 2edca998b..3e36bc6f8 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -99,7 +99,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -134,7 +133,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -169,7 +167,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -211,7 +208,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 15331f633..13b401e4c 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 24 2009 12:19:09 -M5 revision 9bc3e4611009+ 6661+ default tip -M5 started Sep 24 2009 12:19:31 -M5 executing on zooks -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing +M5 compiled Dec 29 2009 23:25:57 +M5 revision b49d467587f8 6811 default processinit.patch qtip tip +M5 started Dec 29 2009 23:25:59 +M5 executing on fajita +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 32409000 because target called exit() +Exiting @ tick 32803000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index 3bfaf3540..d7a673f52 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 303832 # Simulator instruction rate (inst/s) -host_mem_usage 155376 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1703674499 # Simulator tick rate (ticks/s) +host_inst_rate 2804 # Simulator instruction rate (inst/s) +host_mem_usage 203720 # Number of bytes of host memory used +host_seconds 2.08 # Real time elapsed on the host +host_tick_rate 15782115 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5685 # Number of instructions simulated -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 32409000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1133 # number of ReadReq accesses(hits+misses) +sim_insts 5827 # Number of instructions simulated +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 32803000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1051 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.072374 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.072374 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.583333 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2057 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1911 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.070977 # miss rate for demand accesses -system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8456000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses +system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070977 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8003000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2057 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1911 # number of overall hits -system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.070977 # miss rate for overall accesses -system.cpu.dcache.overall_misses 146 # number of overall misses +system.cpu.dcache.overall_hits 1938 # number of overall hits +system.cpu.dcache.overall_miss_latency 8456000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses +system.cpu.dcache.overall_misses 151 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070977 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8003000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.830110 # Cycle average of tags in use -system.cpu.dcache.total_refs 1925 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.887695 # Cycle average of tags in use +system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses @@ -80,57 +80,57 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5687 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55723.684211 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52723.684211 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5383 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16940000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.053455 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 304 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 16028000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17.707237 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5687 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55723.684211 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency -system.cpu.icache.demand_hits 5383 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16940000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.053455 # miss rate for demand accesses -system.cpu.icache.demand_misses 304 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency +system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses +system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 16028000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.053455 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5687 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55723.684211 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5383 # number of overall hits -system.cpu.icache.overall_miss_latency 16940000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.053455 # miss rate for overall accesses -system.cpu.icache.overall_misses 304 # number of overall misses +system.cpu.icache.overall_hits 5526 # number of overall hits +system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses +system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 16028000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.053455 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.394401 # Cycle average of tags in use -system.cpu.icache.total_refs 5383 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 133.475693 # Cycle average of tags in use +system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -143,81 +143,81 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994819 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 384 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15360000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 520000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005405 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995413 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 434 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 434 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22568000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995413 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 434 # number of overall misses +system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 439 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 434 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 370 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 182.412916 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.758016 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 64818 # number of cpu cycles simulated -system.cpu.num_insts 5685 # Number of instructions executed -system.cpu.num_refs 2058 # Number of memory references -system.cpu.workload.PROG:num_syscalls 13 # Number of system calls +system.cpu.numCycles 65606 # number of cpu cycles simulated +system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.num_refs 2090 # Number of memory references +system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- |