Update refs for CPU clock changes and O3 CPI/IPC calculation updates.

tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.out:
tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-timing/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout:
    Update refs.

--HG--
extra : convert_revision : 34a0d18f213386700e2acdd1eb9ebc5fa6daa7f5

8 files changed, 135 insertions, 335 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 59cadaa12..80ef56747 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -1,50 +1,7 @@
 [root]
 type=Root
 children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[debug]
-break_cycles=
-
-[exetrace]
-intel_format=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
 
 [system]
 type=System
@@ -55,7 +12,7 @@ physmem=system.physmem
 [system.cpu]
 type=AtomicSimpleCPU
 children=workload
-clock=1
+clock=500
 cpu_id=0
 defer_registration=false
 function_trace=false
@@ -64,7 +21,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.physmem
+phase=0
 progress_interval=0
 simulate_stalls=false
 system=system
@@ -76,6 +33,7 @@ icache_port=system.membus.port[1]
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
+cwd=
 egid=100
 env=
 euid=100
@@ -92,6 +50,7 @@ uid=100
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
@@ -100,14 +59,6 @@ type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+zero=false
 port=system.membus.port[0]
 
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
index 064f467da..9f8b84468 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
@@ -1,15 +1,13 @@
 [root]
 type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
 
 [system.physmem]
 type=PhysicalMemory
 file=
 range=[0,134217727]
 latency=1
+zero=false
 
 [system]
 type=System
@@ -21,6 +19,7 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
+responder_set=false
 
 [system.cpu.workload]
 type=LiveProcess
@@ -29,6 +28,7 @@ executable=tests/test-progs/hello/bin/mips/linux/hello
 input=cin
 output=cout
 env=
+cwd=
 system=system
 uid=100
 euid=100
@@ -44,64 +44,14 @@ max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
 progress_interval=0
-mem=system.physmem
 system=system
 cpu_id=0
 workload=system.cpu.workload
-clock=1
+clock=500
+phase=0
 defer_registration=false
 width=1
 function_trace=false
 function_trace_start=0
 simulate_stalls=false
 
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-trace_system=client
-
-[debug]
-break_cycles=
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
index 3b2a2730b..daf99515d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  52255                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 148024                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                  52038                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   7127                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 148488                       # Number of bytes of host memory used
+host_seconds                                     0.79                       # Real time elapsed on the host
+host_tick_rate                                3561193                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
-sim_seconds                                  0.000000                       # Number of seconds simulated
-sim_ticks                                        5656                       # Number of ticks simulated
+sim_seconds                                  0.000003                       # Number of seconds simulated
+sim_ticks                                     2828000                       # Number of ticks simulated
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5657                       # number of cpu cycles simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index 600b178b3..b975f8f18 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -6,8 +6,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  9 2006 19:28:25
-M5 started Mon Oct  9 19:28:56 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
-Exiting @ tick 5656 because target called exit()
+M5 compiled Apr 22 2007 20:47:32
+M5 started Sun Apr 22 20:47:35 2007
+M5 executing on zamp.eecs.umich.edu
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 2828000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 8e1bb0388..29fcae5de 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -1,50 +1,7 @@
 [root]
 type=Root
 children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[debug]
-break_cycles=
-
-[exetrace]
-intel_format=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
 
 [system]
 type=System
@@ -55,7 +12,7 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
-clock=1
+clock=500
 cpu_id=0
 defer_registration=false
 function_trace=false
@@ -64,7 +21,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.cpu.dcache
+phase=0
 progress_interval=0
 system=system
 workload=system.cpu.workload
@@ -78,7 +35,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -118,7 +74,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -158,7 +113,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -195,12 +149,14 @@ mem_side=system.membus.port[1]
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
+cwd=
 egid=100
 env=
 euid=100
@@ -217,6 +173,7 @@ uid=100
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.physmem.port system.cpu.l2cache.mem_side
 
@@ -225,14 +182,6 @@ type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+zero=false
 port=system.membus.port[0]
 
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
index d683d2355..d5d160f1e 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
@@ -1,15 +1,13 @@
 [root]
 type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
 
 [system.physmem]
 type=PhysicalMemory
 file=
 range=[0,134217727]
 latency=1
+zero=false
 
 [system]
 type=System
@@ -21,45 +19,7 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+responder_set=false
 
 [system.cpu.workload]
 type=LiveProcess
@@ -68,6 +28,7 @@ executable=tests/test-progs/hello/bin/mips/linux/hello
 input=cin
 output=cout
 env=
+cwd=
 system=system
 uid=100
 euid=100
@@ -83,11 +44,11 @@ max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
 progress_interval=0
-mem=system.cpu.dcache
 system=system
 cpu_id=0
 workload=system.cpu.workload
-clock=1
+clock=500
+phase=0
 defer_registration=false
 // width not specified
 function_trace=false
@@ -99,6 +60,7 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
+responder_set=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -110,7 +72,44 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
 protocol=null
 trace_addr=0
 hash_delay=1
@@ -149,7 +148,6 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
 protocol=null
 trace_addr=0
 hash_delay=1
@@ -178,53 +176,3 @@ prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
 hit_latency=1
 
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-trace_system=client
-
-[debug]
-break_cycles=
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index ae23f7eec..71b0896dd 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  57798                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 179040                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                               17679602                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 224031                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 153864                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+host_tick_rate                              205051803                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
-sim_seconds                                  0.000002                       # Number of seconds simulated
-sim_ticks                                     1738011                       # Number of ticks simulated
+sim_seconds                                  0.000005                       # Number of seconds simulated
+sim_ticks                                     5264500                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses               1130                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3987.109756                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2987.109756                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency  3762.195122                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2762.195122                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                   1048                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency         326943                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency         308500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.072566                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   82                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency       244943                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency       226500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.072566                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              82                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               924                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3968.740000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2968.740000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency         3690                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency         2690                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   874                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency        198437                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency        184500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.054113                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  50                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency       148437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency       134500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.054113                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             50                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                2054                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3980.151515                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2980.151515                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency  3734.848485                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2734.848485                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                    1922                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency          525380                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency          493000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.064265                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   132                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency       393380                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency       361000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.064265                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses              132                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses               2054                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3980.151515                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2980.151515                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_miss_latency  3734.848485                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2734.848485                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1922                       # number of overall hits
-system.cpu.dcache.overall_miss_latency         525380                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency         493000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.064265                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  132                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency       393380                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency       361000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.064265                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             132                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    132                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 82.396200                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 86.050916                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1922                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.icache.ReadReq_accesses               5658                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3978.069307                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2978.069307                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency  3740.924092                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2740.924092                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   5355                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        1205355                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        1133500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.053552                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  303                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency       902355                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency       830500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.053552                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             303                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                5658                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3978.069307                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2978.069307                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency  3740.924092                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2740.924092                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    5355                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         1205355                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         1133500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.053552                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   303                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency       902355                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency       830500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.053552                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              303                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               5658                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3978.069307                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2978.069307                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_miss_latency  3740.924092                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2740.924092                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5355                       # number of overall hits
-system.cpu.icache.overall_miss_latency        1205355                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        1133500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.053552                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  303                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency       902355                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency       830500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.053552                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             303                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     13                       # number of replacements
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                133.062649                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                137.160443                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5355                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadReq_accesses               435                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2983.237875                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1982.237875                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency  2743.648961                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1742.648961                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency       1291742                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency       1188000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.995402                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 433                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency       858309                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency       754567                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995402                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            433                       # number of ReadReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                435                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2983.237875                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1982.237875                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency  2743.648961                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1742.648961                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        1291742                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency        1188000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.995402                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  433                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency       858309                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency       754567                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.995402                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             433                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses               435                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2983.237875                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1982.237875                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_miss_latency  2743.648961                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1742.648961                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       1291742                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency       1188000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.995402                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 433                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency       858309                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency       754567                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.995402                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            433                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   433                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               216.976175                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               224.535228                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                          1738011                       # number of cpu cycles simulated
+system.cpu.numCycles                          5264500                       # number of cpu cycles simulated
 system.cpu.num_insts                             5657                       # Number of instructions executed
 system.cpu.num_refs                              2055                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 8722547ad..1cc143ec3 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 13 2006 18:43:33
-M5 started Fri Oct 13 18:44:16 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
-Exiting @ tick 1738011 because target called exit()
+M5 compiled Apr 22 2007 20:47:32
+M5 started Sun Apr 22 20:47:36 2007
+M5 executing on zamp.eecs.umich.edu
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 5264500 because target called exit()