Update stats for new prefetching fixes.

Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.

8 files changed, 31 insertions, 55 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 83f026450..766c4f486 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -67,9 +67,12 @@ CP0_PerfCtr_W=false
 CP0_SrsCtl_HSS=0
 CP0_WatchHi_M=false
 UnifiedTLB=true
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
@@ -1,3 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 77c8639ab..7b1955a4b 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:37:22
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:37:50
+M5 compiled Feb 16 2009 00:16:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:16:42
 M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello World!
 Exiting @ tick 2828000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 6c370ab2d..20921ce17 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  10079                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 192068                       # Number of bytes of host memory used
-host_seconds                                     0.56                       # Real time elapsed on the host
-host_tick_rate                                5037819                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  24803                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193824                       # Number of bytes of host memory used
+host_seconds                                     0.23                       # Real time elapsed on the host
+host_tick_rate                               12384497                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 9ef900f1f..d6fb3e91a 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -67,9 +67,12 @@ CP0_PerfCtr_W=false
 CP0_SrsCtl_HSS=0
 CP0_WatchHi_M=false
 UnifiedTLB=true
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -99,12 +102,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -136,12 +138,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -173,12 +174,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
@@ -1,3 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index 17fb9f581..a5bd2cd4d 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:37:22
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:37:51
+M5 compiled Feb 16 2009 00:16:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:16:42
 M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello World!
 Exiting @ tick 32322000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index d5658e44c..de10d4a74 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 334992                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199532                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1887416058                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  26568                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201268                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                              151609105                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
 sim_seconds                                  0.000032                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.071081                       # ms
 system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    132                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -135,15 +126,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.053552                       # ms
 system.cpu.icache.overall_mshr_misses             303                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                     13                       # number of replacements
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.995402                       # m
 system.cpu.l2cache.overall_mshr_misses            433                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions