diff options
| author | Korey Sewell <ksewell@umich.edu> | 2009-09-24 12:30:53 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-09-24 12:30:53 -0400 |
| commit | eb1bd7a2e63f09efa7e65bd9dd6578bf9cfd68ac (patch) | |
| tree | deaf8c2317d959f92dfe5727329c7798693c8442 /tests/quick/00.hello/ref/mips/linux | |
| parent | baca1f0566b51a24fda506dc95e3baa6265280d4 (diff) | |
| download | gem5-eb1bd7a2e63f09efa7e65bd9dd6578bf9cfd68ac.tar.xz | |
mips-stats: update regressions of arguments fix
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux')
11 files changed, 429 insertions, 429 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 56a68daea..f04692a1f 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 13 2009 01:40:41 -M5 revision 4c418376e894 6202 default tip -M5 started May 13 2009 01:40:42 +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:46 M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 29437500 because target called exit() +Exiting @ tick 29521500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 577875f3a..a47f185bc 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23976 # Simulator instruction rate (inst/s) -host_mem_usage 152688 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 124659634 # Simulator tick rate (ticks/s) +host_inst_rate 29581 # Simulator instruction rate (inst/s) +host_mem_usage 155804 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 153369596 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29437500 # Number of ticks simulated -system.cpu.AGEN-Unit.instReqsProcessed 2055 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.predictedNotTaken 783 # Number of Branches Predicted As Not Taken (False). +sim_insts 5685 # Number of instructions simulated +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29521500 # Number of ticks simulated +system.cpu.AGEN-Unit.instReqsProcessed 2058 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.predictedNotTaken 789 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 96 # Number of Branches Predicted As Taken (True). -system.cpu.Decode-Unit.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.instReqsProcessed 3598 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 515 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Decode-Unit.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.instReqsProcessed 3624 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 516 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.Execution-Unit.predictedTakenIncorrect 34 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed. system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed. -system.cpu.Fetch-Seq-Unit.instReqsProcessed 11315 # Number of Instructions Requests that completed in this resource. -system.cpu.Graduation-Unit.instReqsProcessed 5656 # Number of Instructions Requests that completed in this resource. +system.cpu.Fetch-Seq-Unit.instReqsProcessed 11373 # Number of Instructions Requests that completed in this resource. +system.cpu.Graduation-Unit.instReqsProcessed 5685 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 10420 # Number of Instructions Requests that completed in this resource. -system.cpu.committedInsts 5656 # Number of Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5656 # Number of Instructions Simulated (Total) -system.cpu.cpi 10.409477 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 10.409477 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) +system.cpu.RegFile-Manager.instReqsProcessed 10479 # Number of Instructions Requests that completed in this resource. +system.cpu.committedInsts 5685 # Number of Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 5685 # Number of Instructions Simulated (Total) +system.cpu.cpi 10.385928 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 10.385928 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1134 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56207.317073 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53207.317073 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4609000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.072502 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.072310 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 4363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.072502 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072310 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 # average WriteReq miss latency @@ -52,48 +52,48 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.568182 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.590909 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2058 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56359.589041 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1909 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1912 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 8228500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.071046 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.070943 # miss rate for demand accesses system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 7790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071046 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.070943 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2058 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56359.589041 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1909 # number of overall hits +system.cpu.dcache.overall_hits 1912 # number of overall hits system.cpu.dcache.overall_miss_latency 8228500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.071046 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.070943 # miss rate for overall accesses system.cpu.dcache.overall_misses 146 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 7790500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071046 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.070943 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.205216 # Cycle average of tags in use -system.cpu.dcache.total_refs 1923 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 84.209307 # Cycle average of tags in use +system.cpu.dcache.total_refs 1926 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache_port.instReqsProcessed 2054 # Number of Instructions Requests that completed in this resource. +system.cpu.dcache_port.instReqsProcessed 2057 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -103,62 +103,62 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55772.277228 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52772.277228 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16899000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15990000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55773.026316 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52773.026316 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5383 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16955000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.053455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 304 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 16043000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 304 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17.707237 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55772.277228 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency -system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16899000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5687 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55773.026316 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52773.026316 # average overall mshr miss latency +system.cpu.icache.demand_hits 5383 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16955000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.053455 # miss rate for demand accesses +system.cpu.icache.demand_misses 304 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15990000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 16043000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.053455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 304 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55772.277228 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5687 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55773.026316 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52773.026316 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 16899000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses -system.cpu.icache.overall_misses 303 # number of overall misses +system.cpu.icache.overall_hits 5383 # number of overall hits +system.cpu.icache.overall_miss_latency 16955000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.053455 # miss rate for overall accesses +system.cpu.icache.overall_misses 304 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15990000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 16043000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.053455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.958324 # Cycle average of tags in use -system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.385131 # Cycle average of tags in use +system.cpu.icache.total_refs 5383 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. -system.cpu.ipc 0.096066 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.096066 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource. +system.cpu.ipc 0.096284 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.096284 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -177,16 +177,16 @@ system.cpu.l2cache.ReadExReq_misses 50 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2004000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52052.219321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.109661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52052.083333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.041667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19936000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15330000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994819 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 384 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52535.714286 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40071.428571 # average UpgradeReq mshr miss latency @@ -198,53 +198,53 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005405 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52103.926097 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52103.686636 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.258065 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22561000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 22613000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995413 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 434 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17334000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17374000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 434 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52103.926097 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52103.686636 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40032.258065 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22561000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 433 # number of overall misses +system.cpu.l2cache.overall_miss_latency 22613000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995413 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 434 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17374000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 434 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 370 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 183.249501 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.672228 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 58876 # number of cpu cycles simulated +system.cpu.numCycles 59044 # number of cpu cycles simulated system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.threadCycles 58876 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 59044 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index 9e32dcc7f..b3bdddcfe 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -412,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 5aef74b1c..9562c954f 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:05:29 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:08 -M5 executing on maize +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:46 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 13881500 because target called exit() +Exiting @ tick 13914500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 6d8206a5c..bdce7b5d3 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 27478 # Simulator instruction rate (inst/s) -host_mem_usage 190884 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 75816661 # Simulator tick rate (ticks/s) +host_inst_rate 59567 # Simulator instruction rate (inst/s) +host_mem_usage 155776 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 163592222 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5024 # Number of instructions simulated +sim_insts 5049 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13881500 # Number of ticks simulated +sim_ticks 13914500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 549 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1924 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 552 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1939 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 721 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1540 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2339 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 384 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 879 # Number of branches committed +system.cpu.BPredUnit.condIncorrect 722 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1555 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2357 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 387 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 885 # Number of branches committed system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14165 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.399223 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14230 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.399438 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.125719 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% 82.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% 90.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% 94.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% 96.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% 98.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% 98.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% 99.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11753 82.59% 82.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1168 8.21% 90.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 499 3.51% 94.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 284 2.00% 96.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 291 2.04% 98.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 72 0.51% 98.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 62 0.44% 99.29% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% 99.56% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 63 0.44% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14165 # Number of insts commited each cycle -system.cpu.commit.COM:count 5655 # Number of instructions committed -system.cpu.commit.COM:loads 1130 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::total 14230 # Number of insts commited each cycle +system.cpu.commit.COM:count 5684 # Number of instructions committed +system.cpu.commit.COM:loads 1133 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2054 # Number of memory references committed +system.cpu.commit.COM:refs 2057 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5655 # The number of committed instructions +system.cpu.commit.branchMispredicts 605 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5684 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 15 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5936 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5024 # Number of Instructions Simulated -system.cpu.committedInsts_total 5024 # Number of Instructions Simulated -system.cpu.cpi 5.526274 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.526274 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2286 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33976.377953 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36034.883721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2159 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4315000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.055556 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 127 # number of ReadReq misses +system.cpu.commit.commitSquashedInsts 5973 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5049 # Number of Instructions Simulated +system.cpu.committedInsts_total 5049 # Number of Instructions Simulated +system.cpu.cpi 5.511983 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.511983 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34007.812500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36022.988506 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2169 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4353000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.055725 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3099000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.037620 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 86 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037875 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27701.724138 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36093.750000 # average WriteReq mshr miss latency @@ -73,54 +73,54 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.970370 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.889706 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3210 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29612.709832 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36060 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2793 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12348500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.129907 # miss rate for demand accesses -system.cpu.dcache.demand_misses 417 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 3221 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29632.775120 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2803 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12386500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.129773 # miss rate for demand accesses +system.cpu.dcache.demand_misses 418 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5409000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.046729 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 5444000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.046880 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3210 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29612.709832 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36060 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 3221 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29632.775120 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2793 # number of overall hits -system.cpu.dcache.overall_miss_latency 12348500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.129907 # miss rate for overall accesses -system.cpu.dcache.overall_misses 417 # number of overall misses +system.cpu.dcache.overall_hits 2803 # number of overall hits +system.cpu.dcache.overall_miss_latency 12386500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.129773 # miss rate for overall accesses +system.cpu.dcache.overall_misses 418 # number of overall misses system.cpu.dcache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5409000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.046729 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 5444000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.046880 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 136 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 87.531358 # Cycle average of tags in use -system.cpu.dcache.total_refs 2831 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.690614 # Cycle average of tags in use +system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 479 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 128 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 128 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14141 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 9863 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3823 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1052 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 14211 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 9912 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3839 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1056 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 251 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -131,116 +131,116 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2339 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2162 # Number of cache lines fetched -system.cpu.fetch.Cycles 6161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Branches 2357 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2171 # Number of cache lines fetched +system.cpu.fetch.Cycles 6187 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 360 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15261 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 737 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.084246 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2162 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.549669 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15217 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.262712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Insts 15337 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 738 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.084693 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.551096 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.003336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.263199 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 11225 73.77% 73.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1766 11.61% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 196 1.29% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 137 0.90% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 314 2.06% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 113 0.74% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 304 2.00% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 249 1.64% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 913 6.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11277 73.77% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1770 11.58% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 198 1.30% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 138 0.90% 87.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 316 2.07% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 114 0.75% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 306 2.00% 92.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 249 1.63% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 918 6.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15217 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 15286 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35436.489607 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1731 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15300500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.199352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 431 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 101 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_hits 1738 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15344000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.199447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 11522000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.152636 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.152004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.245455 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.266667 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2162 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35500 # average overall miss latency +system.cpu.icache.demand_accesses 2171 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35436.489607 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency -system.cpu.icache.demand_hits 1731 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15300500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.199352 # miss rate for demand accesses -system.cpu.icache.demand_misses 431 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 101 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_hits 1738 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15344000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.199447 # miss rate for demand accesses +system.cpu.icache.demand_misses 433 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 11522000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.152636 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.152004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2162 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35500 # average overall miss latency +system.cpu.icache.overall_accesses 2171 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35436.489607 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1731 # number of overall hits -system.cpu.icache.overall_miss_latency 15300500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.199352 # miss rate for overall accesses -system.cpu.icache.overall_misses 431 # number of overall misses -system.cpu.icache.overall_mshr_hits 101 # number of overall MSHR hits +system.cpu.icache.overall_hits 1738 # number of overall hits +system.cpu.icache.overall_miss_latency 15344000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.199447 # miss rate for overall accesses +system.cpu.icache.overall_misses 433 # number of overall misses +system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 11522000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.152636 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.152004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.760808 # Cycle average of tags in use -system.cpu.icache.total_refs 1731 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 159.086288 # Cycle average of tags in use +system.cpu.icache.total_refs 1738 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12547 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:nop 1806 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.291349 # Inst execution rate -system.cpu.iew.EXEC:refs 3420 # number of memory reference insts executed +system.cpu.idleCycles 12544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1216 # Number of branches executed +system.cpu.iew.EXEC:nop 1820 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.292239 # Inst execution rate +system.cpu.iew.EXEC:refs 3432 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1048 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4016 # num instructions consuming a value -system.cpu.iew.WB:count 7315 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.694970 # average fanout of values written-back +system.cpu.iew.WB:consumers 4040 # num instructions consuming a value +system.cpu.iew.WB:count 7355 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.694802 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2791 # num instructions producing a value -system.cpu.iew.WB:rate 0.263471 # insts written-back per cycle -system.cpu.iew.WB:sent 7402 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 661 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2807 # num instructions producing a value +system.cpu.iew.WB:rate 0.264283 # insts written-back per cycle +system.cpu.iew.WB:sent 7444 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2783 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2795 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 15 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 968 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11594 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2372 # Number of load instructions executed +system.cpu.iew.iewDispatchedInsts 11660 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2384 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 531 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8089 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8133 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1052 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1056 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked @@ -250,30 +250,30 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1653 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1662 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 385 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.180954 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.180954 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 386 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.181423 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.181423 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 4988 57.87% 57.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 57.92% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 57.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2560 29.70% 87.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.33% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5020 57.94% 57.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2572 29.69% 87.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.27% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8620 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8664 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018794 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 10 6.17% 6.17% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.17% # attempts to use FU when none available @@ -288,30 +288,30 @@ system.cpu.iq.ISSUE:fu_full::MemRead 98 60.49% 66.67% # at system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15217 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566472 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217507 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15286 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566793 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217668 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 11370 74.72% 74.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1673 10.99% 85.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 787 5.17% 90.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 717 4.71% 95.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 332 2.18% 97.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 198 1.30% 99.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 11421 74.72% 74.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1678 10.98% 85.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 792 5.18% 90.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 722 4.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 333 2.18% 97.78% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 200 1.31% 99.08% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60% 99.68% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15217 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.310474 # Inst issue rate -system.cpu.iq.iqInstsAdded 9773 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8620 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15286 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.311319 # Inst issue rate +system.cpu.iq.iqInstsAdded 9825 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8664 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4182 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 4207 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 30 # Number of squashed instructions issued -system.cpu.iq.iqSquashedOperandsExamined 2741 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -330,16 +330,16 @@ system.cpu.l2cache.ReadExReq_misses 49 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 1539000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 49 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34308.252427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.854369 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34307.506053 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.750605 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14135000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990385 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12825500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990385 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 14169000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12857000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 34400 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31166.666667 # average UpgradeReq mshr miss latency @@ -351,68 +351,68 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010076 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010050 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 465 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34350.325380 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 466 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34349.567100 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15835500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.991398 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 461 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 15869500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.991416 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 462 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14364500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.991398 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 14396000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.991416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 462 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 465 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34350.325380 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 466 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34349.567100 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15835500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.991398 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 461 # number of overall misses +system.cpu.l2cache.overall_miss_latency 15869500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.991416 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 462 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14364500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.991398 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 14396000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.991416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 397 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 208.689672 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 209.158769 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2795 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 27764 # number of cpu cycles simulated +system.cpu.numCycles 27830 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 20 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 3304 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10242 # Number of cycles rename is idle +system.cpu.rename.RENAME:CommittedMaps 3323 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 10291 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15583 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13384 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8214 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3446 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1052 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 15666 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13454 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8251 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3462 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1056 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 29 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4910 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 4928 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 428 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 125 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed -system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 5d677c743..296171530 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -111,7 +111,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index b140ca5f4..77cc5d321 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:01:16 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:01:42 -M5 executing on zizzer +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:47 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 2828000 because target called exit() +Exiting @ tick 2842500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index 60efc35e1..d36fc469a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 525065 # Simulator instruction rate (inst/s) -host_mem_usage 193736 # Number of bytes of host memory used +host_inst_rate 588083 # Simulator instruction rate (inst/s) +host_mem_usage 149516 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 257090909 # Simulator tick rate (ticks/s) +host_tick_rate 285563593 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated +sim_insts 5685 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2828000 # Number of ticks simulated +sim_ticks 2842500 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,9 +28,9 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5657 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references +system.cpu.numCycles 5686 # number of cpu cycles simulated +system.cpu.num_insts 5685 # Number of instructions executed +system.cpu.num_refs 2058 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 9f3729e92..2edca998b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -211,7 +211,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 7d691a50e..15331f633 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:36 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:19:48 -M5 executing on maize +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:31 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 32322000 because target called exit() +Exiting @ tick 32409000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index 8e4a1aeed..3bfaf3540 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,22 +1,22 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198393 # Simulator instruction rate (inst/s) -host_mem_usage 202876 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 1123305762 # Simulator tick rate (ticks/s) +host_inst_rate 303832 # Simulator instruction rate (inst/s) +host_mem_usage 155376 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1703674499 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated +sim_insts 5685 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 32322000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) +sim_ticks 32409000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1133 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1051 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.072374 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072374 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency @@ -30,45 +30,45 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.583333 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2057 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1911 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.070977 # miss rate for demand accesses system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.070977 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2057 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1908 # number of overall hits +system.cpu.dcache.overall_hits 1911 # number of overall hits system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.070977 # miss rate for overall accesses system.cpu.dcache.overall_misses 146 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.070977 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use -system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.830110 # Cycle average of tags in use +system.cpu.dcache.total_refs 1925 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses @@ -80,57 +80,57 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55723.684211 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52723.684211 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5383 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16940000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.053455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 304 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 16028000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 304 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17.707237 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5687 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55723.684211 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency +system.cpu.icache.demand_hits 5383 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16940000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.053455 # miss rate for demand accesses +system.cpu.icache.demand_misses 304 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 16028000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.053455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 304 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5687 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55723.684211 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses -system.cpu.icache.overall_misses 303 # number of overall misses +system.cpu.icache.overall_hits 5383 # number of overall hits +system.cpu.icache.overall_miss_latency 16940000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.053455 # miss rate for overall accesses +system.cpu.icache.overall_misses 304 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 16028000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.053455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use -system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 135.394401 # Cycle average of tags in use +system.cpu.icache.total_refs 5383 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -152,16 +152,16 @@ system.cpu.l2cache.ReadExReq_misses 50 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19968000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994819 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 384 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -173,51 +173,51 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005405 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995413 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 434 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 434 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 433 # number of overall misses +system.cpu.l2cache.overall_miss_latency 22568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995413 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 434 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 434 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 370 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 182.412916 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 64644 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references +system.cpu.numCycles 64818 # number of cpu cycles simulated +system.cpu.num_insts 5685 # Number of instructions executed +system.cpu.num_refs 2058 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- |