Update REFs for statistics patch in cache

--HG--
extra : convert_revision : 8987d3ab62ea4b2fa18ebd40fc980b30561d7e45

2 files changed, 22 insertions, 22 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index e497ba79b..54771832b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,28 +1,28 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  67697                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 158936                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                                 102046                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 289509                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 158964                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                                 429531                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
 sim_ticks                                        8573                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses               1131                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 1791574296802328064                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency            3                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency            2                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                   1052                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   141534369447383908352                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency            237                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.069850                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   79                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_miss_latency          158                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.069850                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              79                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               933                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2766176443076198912                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency     2.586207                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency            2                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   875                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  160438233698419539968                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency           150                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.062165                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  58                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_miss_latency          100                       # number of WriteReq MSHR miss cycles
@@ -37,10 +37,10 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                2064                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2204179585005864704                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency     2.824818                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency            2                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                    1927                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    301972603145803464704                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency             387                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.066376                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   137                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
@@ -51,11 +51,11 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses               2064                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2204179585005864704                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency     2.824818                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1927                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   301972603145803464704                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency            387                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.066376                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  137                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
@@ -81,17 +81,17 @@ system.cpu.dcache.total_refs                     1927                       # To
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.icache.ReadReq_accesses               5658                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 1549898021785231104                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency     2.993399                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency     1.993399                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   5355                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency   469619100600925028352                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency            907                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.053552                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  303                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_miss_latency          604                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.053552                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             303                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_refs                  17.673267                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
@@ -99,10 +99,10 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                5658                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 1549898021785231104                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency     2.993399                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency     1.993399                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    5355                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency    469619100600925028352                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency             907                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.053552                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   303                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
@@ -113,11 +113,11 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               5658                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 1549898021785231104                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency     2.993399                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency     1.993399                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5355                       # number of overall hits
-system.cpu.icache.overall_miss_latency   469619100600925028352                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency            907                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.053552                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  303                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index b9431269e..fd27ee686 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 18 2006 00:09:15
-M5 started Fri Aug 18 00:12:56 2006
+M5 compiled Aug 21 2006 14:43:46
+M5 started Mon Aug 21 14:44:00 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Exiting @ tick 8573 because target called exit()