Bus: Update the stats for the recent bus fix.

--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407

4 files changed, 156 insertions, 54 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 7da6cb048..1b246149f 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -11,7 +11,62 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache itb l2cache tlb toL2Bus tracer workload
+CP0_Config=0
+CP0_Config1=0
+CP0_Config1_C2=false
+CP0_Config1_CA=false
+CP0_Config1_DA=0
+CP0_Config1_DL=0
+CP0_Config1_DS=0
+CP0_Config1_EP=false
+CP0_Config1_FP=false
+CP0_Config1_IA=0
+CP0_Config1_IL=0
+CP0_Config1_IS=0
+CP0_Config1_M=0
+CP0_Config1_MD=false
+CP0_Config1_MMU=0
+CP0_Config1_PC=false
+CP0_Config1_WR=false
+CP0_Config2=0
+CP0_Config2_M=false
+CP0_Config2_SA=0
+CP0_Config2_SL=0
+CP0_Config2_SS=0
+CP0_Config2_SU=0
+CP0_Config2_TA=0
+CP0_Config2_TL=0
+CP0_Config2_TS=0
+CP0_Config2_TU=0
+CP0_Config3=0
+CP0_Config3_DSPP=false
+CP0_Config3_LPA=false
+CP0_Config3_M=false
+CP0_Config3_MT=false
+CP0_Config3_SM=false
+CP0_Config3_SP=false
+CP0_Config3_TL=false
+CP0_Config3_VEIC=false
+CP0_Config3_VInt=false
+CP0_Config_AR=0
+CP0_Config_AT=0
+CP0_Config_BE=0
+CP0_Config_MT=0
+CP0_Config_VI=0
+CP0_EBase_CPUNum=0
+CP0_IntCtl_IPPCI=0
+CP0_IntCtl_IPTI=0
+CP0_PRId=0
+CP0_PRId_CompanyID=0
+CP0_PRId_CompanyOptions=0
+CP0_PRId_ProcessorID=1
+CP0_PRId_Revision=0
+CP0_PerfCtr_M=false
+CP0_PerfCtr_W=false
+CP0_SrsCtl_HSS=0
+CP0_WatchHi_M=false
+UnifiedTLB=true
 clock=500
 cpu_id=0
 defer_registration=false
@@ -26,6 +81,7 @@ max_loads_any_thread=0
 phase=0
 progress_interval=0
 system=system
+tlb=system.cpu.tlb
 tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -69,6 +125,7 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=MipsDTB
+size=64
 
 [system.cpu.icache]
 type=BaseCache
@@ -108,6 +165,7 @@ mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
 type=MipsITB
+size=64
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -145,11 +203,16 @@ write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
 mem_side=system.membus.port[1]
 
+[system.cpu.tlb]
+type=MipsUTB
+size=64
+
 [system.cpu.toL2Bus]
 type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
@@ -167,6 +230,7 @@ euid=100
 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
@@ -178,6 +242,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.l2cache.mem_side
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index c7e605dd3..d3bab9d0b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 192479                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197496                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                              618816195                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  11117                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195308                       # Number of bytes of host memory used
+host_seconds                                     0.51                       # Real time elapsed on the host
+host_tick_rate                               38035865                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
-sim_seconds                                  0.000018                       # Number of seconds simulated
-sim_ticks                                    18463000                       # Number of ticks simulated
+sim_seconds                                  0.000019                       # Number of seconds simulated
+sim_ticks                                    19359000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses               1130                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency        27000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency        24000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                   1048                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        2050000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency        2214000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.072566                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   82                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      1886000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      1968000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.072566                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              82                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               924                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        27000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        24000                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   860                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       1600000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       1728000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.069264                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  64                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      1472000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      1536000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.069264                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             64                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                2054                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency        25000                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency        27000                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                    1908                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         3650000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency         3942000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.071081                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   146                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      3358000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      3504000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.071081                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses              146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses               2054                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency        25000                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency        27000                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1908                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        3650000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency        3942000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.071081                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  146                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      3358000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      3504000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.071081                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,18 +76,27 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    132                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 84.706280                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 84.621729                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1922                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
 system.cpu.icache.ReadReq_accesses               5658                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24920.792079                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 22920.792079                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 26914.191419                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23914.191419                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   5355                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        7551000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        8155000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.053552                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  303                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      6945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      7246000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.053552                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             303                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -99,29 +108,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                5658                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24920.792079                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 22920.792079                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 26914.191419                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23914.191419                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    5355                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         7551000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         8155000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.053552                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   303                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      6945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      7246000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.053552                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              303                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               5658                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24920.792079                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 22920.792079                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 26914.191419                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23914.191419                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5355                       # number of overall hits
-system.cpu.icache.overall_miss_latency        7551000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        8155000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.053552                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  303                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      6945000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      7246000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.053552                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             303                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -138,34 +147,43 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     13                       # number of replacements
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                135.936693                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                135.855992                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5355                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses              50                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      1100000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1150000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses                50                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency       550000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses               385                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency       8426000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency       8809000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.994805                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 383                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency      4213000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994805                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            383                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses             14                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        22000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        23000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency       308000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency       322000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses               14                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency       154000                       # number of UpgradeReq MSHR miss cycles
@@ -180,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                435                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        9526000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency        9959000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.995402                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  433                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -194,11 +212,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses               435                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       9526000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency       9959000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.995402                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 433                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -219,14 +237,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               183.281817                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               183.190154                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            36926                       # number of cpu cycles simulated
+system.cpu.numCycles                            38718                       # number of cpu cycles simulated
 system.cpu.num_insts                             5656                       # Number of instructions executed
 system.cpu.num_refs                              2055                       # Number of memory references
+system.cpu.tlb.accesses                             0                       # DTB accesses
+system.cpu.tlb.accesses                             0                       # DTB accesses
+system.cpu.tlb.hits                                 0                       # DTB hits
+system.cpu.tlb.hits                                 0                       # DTB hits
+system.cpu.tlb.misses                               0                       # DTB misses
+system.cpu.tlb.misses                               0                       # DTB misses
+system.cpu.tlb.read_accesses                        0                       # DTB read accesses
+system.cpu.tlb.read_accesses                        0                       # DTB read accesses
+system.cpu.tlb.read_hits                            0                       # DTB read hits
+system.cpu.tlb.read_hits                            0                       # DTB read hits
+system.cpu.tlb.read_misses                          0                       # DTB read misses
+system.cpu.tlb.read_misses                          0                       # DTB read misses
+system.cpu.tlb.write_accesses                       0                       # DTB write accesses
+system.cpu.tlb.write_accesses                       0                       # DTB write accesses
+system.cpu.tlb.write_hits                           0                       # DTB write hits
+system.cpu.tlb.write_hits                           0                       # DTB write hits
+system.cpu.tlb.write_misses                         0                       # DTB write misses
+system.cpu.tlb.write_misses                         0                       # DTB write misses
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr
index f33d007a7..5992f7131 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr
@@ -1,2 +1,3 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 08628c4d1..4dcddd5ae 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -1,14 +1,14 @@
 Hello World!
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 14 2007 22:02:23
-M5 started Tue Aug 14 22:02:25 2007
-M5 executing on nacho
+M5 compiled Feb 24 2008 13:24:29
+M5 started Sun Feb 24 13:24:31 2008
+M5 executing on tater
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 18463000 because target called exit()
+Exiting @ tick 19359000 because target called exit()