tests: new ref outputs for new cache model

--HG--
extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6

6 files changed, 90 insertions, 76 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index ea3ba751b..c6807e6a7 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=workload
+children=tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
@@ -25,11 +25,15 @@ phase=0
 progress_interval=0
 simulate_stalls=false
 system=system
+tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
 dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
+[system.cpu.tracer]
+type=ExeTracer
+
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
@@ -53,7 +57,7 @@ bus_id=0
 clock=1000
 responder_set=false
 width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
index 6a0c251b5..98d540d90 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 535701                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 148368                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              257653061                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  25511                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 149560                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
+host_tick_rate                               12728361                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index 7fb23e5a5..3919c7c81 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 15 2007 12:54:05
-M5 started Tue May 15 12:54:07 2007
+M5 compiled Aug  3 2007 04:06:41
+M5 started Fri Aug  3 04:31:09 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index a5d4e6583..c52036289 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
@@ -24,17 +24,16 @@ max_loads_any_thread=0
 phase=0
 progress_interval=0
 system=system
+tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=1000
 lifo=false
@@ -44,7 +43,7 @@ prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
 prefetch_miss=false
 prefetch_past_page=false
 prefetch_policy=none
@@ -52,12 +51,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=262144
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -68,11 +65,9 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.icache]
 type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=1000
 lifo=false
@@ -82,7 +77,7 @@ prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
 prefetch_miss=false
 prefetch_past_page=false
 prefetch_policy=none
@@ -90,12 +85,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=131072
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -106,11 +99,9 @@ mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=10000
 lifo=false
@@ -120,7 +111,7 @@ prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
 prefetch_miss=false
 prefetch_past_page=false
 prefetch_policy=none
@@ -128,12 +119,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=2097152
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -151,6 +140,9 @@ responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
+[system.cpu.tracer]
+type=ExeTracer
+
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
@@ -174,7 +166,7 @@ bus_id=0
 clock=1000
 responder_set=false
 width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index 41bb7c8b7..985175cad 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 273338                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 153844                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              633390216                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  45085                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 155088                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                              101545982                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
-sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    13362000                       # Number of ticks simulated
+sim_seconds                                  0.000014                       # Number of seconds simulated
+sim_ticks                                    13544000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses               1130                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency        14000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency        13000                       # average ReadReq mshr miss latency
@@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses              82                       # nu
 system.cpu.dcache.WriteReq_accesses               924                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        14000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        13000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   874                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency        700000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.054113                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                  50                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency       650000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.054113                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             50                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits                   860                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency        896000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.069264                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                  64                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency       832000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.069264                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses             64                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  14.560606                       # Average number of references to valid blocks.
@@ -39,14 +39,14 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.demand_accesses                2054                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency        14000                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency        13000                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    1922                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         1848000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.064265                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   132                       # number of demand (read+write) misses
+system.cpu.dcache.demand_hits                    1908                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         2044000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.071081                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   146                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      1716000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.064265                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              132                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency      1898000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.071081                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
@@ -54,14 +54,14 @@ system.cpu.dcache.overall_accesses               2054                       # nu
 system.cpu.dcache.overall_avg_miss_latency        14000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        13000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   1922                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        1848000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.064265                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  132                       # number of overall misses
+system.cpu.dcache.overall_hits                   1908                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        2044000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.071081                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  146                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      1716000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.064265                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             132                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency      1898000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.071081                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    132                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 85.283494                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 85.440937                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1922                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
@@ -138,34 +138,52 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     13                       # number of replacements
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                136.309471                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                136.727640                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5355                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses               435                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        13000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses              50                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency        12000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency       600000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses                50                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency       550000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses           50                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses               385                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency        12000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency       5629000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.995402                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 433                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      4763000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995402                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            433                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency       4596000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.994805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 383                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency      4213000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            383                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses             14                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        12000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency       168000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses               14                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       154000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses           14                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.004619                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.005420                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                435                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        12000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        5629000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency        5196000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.995402                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  433                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -176,11 +194,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses               435                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        12000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       5629000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency       5196000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.995402                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 433                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -199,14 +217,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   433                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               222.872415                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               184.077317                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         13362000                       # number of cpu cycles simulated
+system.cpu.numCycles                         13544000                       # number of cpu cycles simulated
 system.cpu.num_insts                             5657                       # Number of instructions executed
 system.cpu.num_refs                              2055                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 6b688641a..c24f82c4f 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 15 2007 12:54:05
-M5 started Tue May 15 12:54:07 2007
+M5 compiled Aug  3 2007 04:06:41
+M5 started Fri Aug  3 04:31:10 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 13362000 because target called exit()
+Exiting @ tick 13544000 because target called exit()