Update stats for change in functional path in cache

--HG--
extra : convert_revision : 5abc964ca95b80522266c5c1bc5e661d41f2798a

2 files changed, 77 insertions, 75 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index 5d054b950..bc5ad3cca 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,67 +1,67 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 129834                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 158964                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
-host_tick_rate                                 194881                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 273933                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159012                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                                 403699                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
-sim_ticks                                        8573                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses               1131                       # number of ReadReq accesses(hits+misses)
+sim_ticks                                        8579                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses               1130                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency            3                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency            2                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                   1052                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency            237                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.069850                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                   79                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency          158                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.069850                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses              79                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses               933                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency     2.586207                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_hits                   1048                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency            246                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.072566                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                   82                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency          164                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.072566                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses              82                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses               924                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency            3                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency            2                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   875                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits                   874                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency           150                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.062165                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                  58                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate         0.054113                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                  50                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_miss_latency          100                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.053591                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.054113                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             50                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  14.065693                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  14.560606                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                2064                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency     2.824818                       # average overall miss latency
+system.cpu.dcache.demand_accesses                2054                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency            3                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency            2                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    1927                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency             387                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.066376                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   137                       # number of demand (read+write) misses
+system.cpu.dcache.demand_hits                    1922                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency             396                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.064265                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   132                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency          258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.062500                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              129                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency          264                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.064265                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              132                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses               2064                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency     2.824818                       # average overall miss latency
+system.cpu.dcache.overall_accesses               2054                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency            3                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   1927                       # number of overall hits
-system.cpu.dcache.overall_miss_latency            387                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.066376                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  137                       # number of overall misses
+system.cpu.dcache.overall_hits                   1922                       # number of overall hits
+system.cpu.dcache.overall_miss_latency            396                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.064265                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  132                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency          258                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.062500                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             129                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency          264                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.064265                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             132                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    137                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                    132                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 91.822487                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1927                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 86.924009                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1922                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.icache.ReadReq_accesses               5658                       # number of ReadReq accesses(hits+misses)
@@ -138,55 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     13                       # number of replacements
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                138.188010                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                138.192774                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5355                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses               440                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency     1.963470                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_accesses               435                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency            2                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency            1                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency           860                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.995455                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 438                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency          430                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.977273                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            430                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency           866                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.995402                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 433                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency          433                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995402                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            433                       # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReq_accesses                1                       # number of WriteReq accesses(hits+misses)
+system.cpu.l2cache.WriteReq_hits                    1                       # number of WriteReq hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.004566                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.006928                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                440                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency     1.963470                       # average overall miss latency
+system.cpu.l2cache.demand_accesses                436                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency            860                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.995455                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  438                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency            866                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.993119                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                  433                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency          430                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.977273                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             430                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency          433                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.993119                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses             433                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses               440                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency     1.963470                       # average overall miss latency
+system.cpu.l2cache.overall_accesses               436                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency           860                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.995455                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 438                       # number of overall misses
+system.cpu.l2cache.overall_hits                     3                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency           866                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.993119                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                 433                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency          430                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.977273                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            430                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency          433                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.993119                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses            433                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -199,10 +201,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   438                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   433                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               231.300093                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               226.406294                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 11009935d..954193ee0 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep  5 2006 15:37:09
-M5 started Tue Sep  5 15:46:32 2006
+M5 compiled Oct  7 2006 12:52:26
+M5 started Sat Oct  7 12:52:42 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
-Exiting @ tick 8573 because target called exit()
+Exiting @ tick 8579 because target called exit()