Regression: Update stats for cache changes.

--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1

3 files changed, 58 insertions, 52 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index c52036289..f2dee3856 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -34,10 +34,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=2
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -68,10 +70,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=2
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -102,10 +106,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=2
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index 985175cad..a9c46636a 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  45085                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 155088                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-host_tick_rate                              101545982                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 269189                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197500                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                              866482072                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
-sim_seconds                                  0.000014                       # Number of seconds simulated
-sim_ticks                                    13544000                       # Number of ticks simulated
+sim_seconds                                  0.000018                       # Number of seconds simulated
+sim_ticks                                    18463000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses               1130                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency        14000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        13000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                   1048                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        1148000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency        2050000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.072566                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   82                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      1066000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      1886000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.072566                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              82                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               924                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        14000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        13000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   860                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency        896000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       1600000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.069264                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  64                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency       832000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      1472000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.069264                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             64                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                2054                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency        14000                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        13000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency        25000                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                    1908                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         2044000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency         3650000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.071081                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   146                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      1898000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      3358000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.071081                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses              146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses               2054                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency        14000                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        13000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency        25000                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1908                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        2044000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency        3650000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.071081                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  146                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      1898000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      3358000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.071081                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    132                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 85.440937                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 84.706280                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1922                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.icache.ReadReq_accesses               5658                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13986.798680                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24920.792079                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22920.792079                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   5355                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        4238000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        7551000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.053552                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  303                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      3935000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      6945000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.053552                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             303                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                5658                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13986.798680                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24920.792079                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22920.792079                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    5355                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         4238000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         7551000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.053552                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   303                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      3935000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      6945000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.053552                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              303                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               5658                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13986.798680                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24920.792079                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22920.792079                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5355                       # number of overall hits
-system.cpu.icache.overall_miss_latency        4238000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        7551000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.053552                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  303                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      3935000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      6945000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.053552                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             303                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     13                       # number of replacements
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                136.727640                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                135.936693                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5355                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadExReq_accesses              50                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        12000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency       600000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1100000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses                50                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency       550000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses               385                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        12000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency       4596000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency       8426000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.994805                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 383                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency      4213000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994805                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            383                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses             14                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        12000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        22000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency       168000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency       308000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses               14                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency       154000                       # number of UpgradeReq MSHR miss cycles
@@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                435                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        12000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        5196000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency        9526000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.995402                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  433                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses               435                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        12000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       5196000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency       9526000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.995402                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 433                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               184.077317                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               183.281817                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         13544000                       # number of cpu cycles simulated
+system.cpu.numCycles                         18463000                       # number of cpu cycles simulated
 system.cpu.num_insts                             5657                       # Number of instructions executed
 system.cpu.num_refs                              2055                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index c24f82c4f..ad6e002b5 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  3 2007 04:06:41
-M5 started Fri Aug  3 04:31:10 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 17:11:48
+M5 started Sun Aug 12 17:11:50 2007
+M5 executing on zeep
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 13544000 because target called exit()
+Exiting @ tick 18463000 because target called exit()