diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/quick/00.hello/ref/mips | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/quick/00.hello/ref/mips')
15 files changed, 253 insertions, 518 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index 5ba5eb09f..75367618d 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -23,60 +23,6 @@ type=InOrderCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 -CP0_Config=0 -CP0_Config1=0 -CP0_Config1_C2=false -CP0_Config1_CA=false -CP0_Config1_DA=0 -CP0_Config1_DL=0 -CP0_Config1_DS=0 -CP0_Config1_EP=false -CP0_Config1_FP=false -CP0_Config1_IA=0 -CP0_Config1_IL=0 -CP0_Config1_IS=0 -CP0_Config1_M=0 -CP0_Config1_MD=false -CP0_Config1_MMU=0 -CP0_Config1_PC=false -CP0_Config1_WR=false -CP0_Config2=0 -CP0_Config2_M=false -CP0_Config2_SA=0 -CP0_Config2_SL=0 -CP0_Config2_SS=0 -CP0_Config2_SU=0 -CP0_Config2_TA=0 -CP0_Config2_TL=0 -CP0_Config2_TS=0 -CP0_Config2_TU=0 -CP0_Config3=0 -CP0_Config3_DSPP=false -CP0_Config3_LPA=false -CP0_Config3_M=false -CP0_Config3_MT=false -CP0_Config3_SM=false -CP0_Config3_SP=false -CP0_Config3_TL=false -CP0_Config3_VEIC=false -CP0_Config3_VInt=false -CP0_Config_AR=0 -CP0_Config_AT=0 -CP0_Config_BE=0 -CP0_Config_MT=0 -CP0_Config_VI=0 -CP0_EBase_CPUNum=0 -CP0_IntCtl_IPPCI=0 -CP0_IntCtl_IPTI=0 -CP0_PRId=0 -CP0_PRId_CompanyID=0 -CP0_PRId_CompanyOptions=0 -CP0_PRId_ProcessorID=1 -CP0_PRId_Revision=0 -CP0_PerfCtr_M=false -CP0_PerfCtr_W=false -CP0_SrsCtl_HSS=0 -CP0_WatchHi_M=false RASSize=16 activity=0 cachePorts=2 @@ -140,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -175,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -210,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 41a76071a..99ccb1cf2 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 18 2011 18:35:15 -M5 revision Unknown -M5 started Feb 18 2011 18:52:36 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 12:18:54 +M5 started Apr 19 2011 12:19:08 +M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index ac0fe4aec..d39207b30 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 94112 # Simulator instruction rate (inst/s) -host_mem_usage 191540 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 346291258 # Simulator tick rate (ticks/s) +host_inst_rate 121226 # Simulator instruction rate (inst/s) +host_mem_usage 203988 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 446414211 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated sim_ticks 21538000 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 2404 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 14.054054 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 26 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 185 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 844 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 778 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 3261 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 92.139738 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 844 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 72 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 812 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10004 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 6594 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic system.cpu.activity 13.954082 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 2404 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 14.054054 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 26 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 185 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 844 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 778 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1066 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.comBranches 916 # Number of Branches instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 138 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021745 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 89.067186 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021745 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56295.580110 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency @@ -120,6 +108,12 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.execution_unit.executions 3261 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 92.139738 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 844 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 72 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 812 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55527.559055 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812 # average ReadReq mshr miss latency @@ -153,8 +147,8 @@ system.cpu.icache.demand_mshr_misses 319 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.070945 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 145.295903 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.070945 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55527.559055 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency @@ -229,8 +223,8 @@ system.cpu.l2cache.demand_mshr_misses 455 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006169 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 202.151439 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006169 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52370.329670 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency @@ -252,31 +246,37 @@ system.cpu.l2cache.tagsinuse 202.151439 # Cy system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.numCycles 43077 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 10004 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 6594 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 3410 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 6011 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 39203 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 3874 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 8.993198 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 40159 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 2918 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 6.773916 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 40245 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 2832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 6.574274 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 41757 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 1320 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.064280 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 39874 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 3203 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 7.435522 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 39203 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3874 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 8.993198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40159 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2918 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 6.773916 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 40245 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2832 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 6.574274 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41757 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1320 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.064280 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39874 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3203 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.435522 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 10193 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.workload.num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index f2ed87236..5fbba49b2 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -23,62 +23,10 @@ type=DerivO3CPU children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 -CP0_Config=0 -CP0_Config1=0 -CP0_Config1_C2=false -CP0_Config1_CA=false -CP0_Config1_DA=0 -CP0_Config1_DL=0 -CP0_Config1_DS=0 -CP0_Config1_EP=false -CP0_Config1_FP=false -CP0_Config1_IA=0 -CP0_Config1_IL=0 -CP0_Config1_IS=0 -CP0_Config1_M=0 -CP0_Config1_MD=false -CP0_Config1_MMU=0 -CP0_Config1_PC=false -CP0_Config1_WR=false -CP0_Config2=0 -CP0_Config2_M=false -CP0_Config2_SA=0 -CP0_Config2_SL=0 -CP0_Config2_SS=0 -CP0_Config2_SU=0 -CP0_Config2_TA=0 -CP0_Config2_TL=0 -CP0_Config2_TS=0 -CP0_Config2_TU=0 -CP0_Config3=0 -CP0_Config3_DSPP=false -CP0_Config3_LPA=false -CP0_Config3_M=false -CP0_Config3_MT=false -CP0_Config3_SM=false -CP0_Config3_SP=false -CP0_Config3_TL=false -CP0_Config3_VEIC=false -CP0_Config3_VInt=false -CP0_Config_AR=0 -CP0_Config_AT=0 -CP0_Config_BE=0 -CP0_Config_MT=0 -CP0_Config_VI=0 -CP0_EBase_CPUNum=0 -CP0_IntCtl_IPPCI=0 -CP0_IntCtl_IPTI=0 -CP0_PRId=0 -CP0_PRId_CompanyID=0 -CP0_PRId_CompanyOptions=0 -CP0_PRId_ProcessorID=1 -CP0_PRId_Revision=0 -CP0_PerfCtr_M=false -CP0_PerfCtr_W=false -CP0_SrsCtl_HSS=0 -CP0_WatchHi_M=false LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 27c18cbea..5852e6d08 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 23:01:20 -M5 started Mar 17 2011 23:01:33 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:18:54 +M5 started Apr 19 2011 12:19:08 +M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 81b1a48e3..cdb83d87c 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 71769 # Simulator instruction rate (inst/s) -host_mem_usage 206840 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 176990793 # Simulator tick rate (ticks/s) +host_inst_rate 109180 # Simulator instruction rate (inst/s) +host_mem_usage 204504 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 269299917 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 380 # Nu system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 1716 # Number of BP lookups system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 77 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12220 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.476759 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12220 # Number of insts commited each cycle -system.cpu.commit.COM:count 5826 # Number of instructions committed -system.cpu.commit.COM:fp_insts 2 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 87 # Number of function calls committed. -system.cpu.commit.COM:int_insts 5124 # Number of committed integer instructions. -system.cpu.commit.COM:loads 1164 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2089 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted +system.cpu.commit.branches 916 # Number of branches committed +system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle +system.cpu.commit.count 5826 # Number of instructions committed +system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. +system.cpu.commit.function_calls 87 # Number of function calls committed. +system.cpu.commit.int_insts 5124 # Number of committed integer instructions. +system.cpu.commit.loads 1164 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 2089 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 141 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022393 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency @@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse 91.720291 # Cy system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 742 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 89 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10279 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8753 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2688 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 636 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 153 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 37 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle +system.cpu.decode.RunCycles 2688 # Number of cycles decode is running +system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -200,8 +200,8 @@ system.cpu.icache.demand_mshr_misses 329 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077515 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency @@ -224,21 +224,13 @@ system.cpu.icache.total_refs 1129 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1171 # Number of branches executed -system.cpu.iew.EXEC:nop 1220 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.276575 # Inst execution rate -system.cpu.iew.EXEC:refs 2915 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1038 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 3566 # num instructions consuming a value -system.cpu.iew.WB:count 6732 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.716489 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2555 # num instructions producing a value -system.cpu.iew.WB:rate 0.263092 # insts written-back per cycle -system.cpu.iew.WB:sent 6801 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 1171 # Number of branches executed +system.cpu.iew.exec_nop 1220 # number of nop insts executed +system.cpu.iew.exec_rate 0.276575 # Inst execution rate +system.cpu.iew.exec_refs 2915 # number of memory reference insts executed +system.cpu.iew.exec_stores 1038 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions @@ -266,103 +258,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 202 # system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 3566 # num instructions consuming a value +system.cpu.iew.wb_count 6732 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 2555 # num instructions producing a value +system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle +system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 9689 # number of integer regfile reads system.cpu.int_regfile_writes 4703 # number of integer regfile writes system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1952 26.77% 85.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1047 14.36% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 7293 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 143 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 12856 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567284 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 12856 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.285016 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1952 26.77% 85.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1047 14.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 7293 # Type of FU issued system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 143 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses @@ -373,6 +355,24 @@ system.cpu.iq.iqNonSpecInstsAdded 10 # Nu system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle +system.cpu.iq.rate 0.285016 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -423,8 +423,8 @@ system.cpu.l2cache.demand_mshr_misses 467 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006657 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency @@ -454,26 +454,26 @@ system.cpu.misc_regfile_reads 134 # nu system.cpu.numCycles 25588 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 8904 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 11929 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 9880 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 6029 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2577 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 636 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 2619 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 5 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 11924 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 15 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 193 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed +system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 2577 # Number of cycles rename is running +system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 15 # count of serializing insts renamed +system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 21319 # The number of ROB reads system.cpu.rob.rob_writes 19020 # The number of ROB writes system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.workload.num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 8a615b31d..9c80192e1 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -21,60 +21,6 @@ work_item_id=-1 [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload -CP0_Config=0 -CP0_Config1=0 -CP0_Config1_C2=false -CP0_Config1_CA=false -CP0_Config1_DA=0 -CP0_Config1_DL=0 -CP0_Config1_DS=0 -CP0_Config1_EP=false -CP0_Config1_FP=false -CP0_Config1_IA=0 -CP0_Config1_IL=0 -CP0_Config1_IS=0 -CP0_Config1_M=0 -CP0_Config1_MD=false -CP0_Config1_MMU=0 -CP0_Config1_PC=false -CP0_Config1_WR=false -CP0_Config2=0 -CP0_Config2_M=false -CP0_Config2_SA=0 -CP0_Config2_SL=0 -CP0_Config2_SS=0 -CP0_Config2_SU=0 -CP0_Config2_TA=0 -CP0_Config2_TL=0 -CP0_Config2_TS=0 -CP0_Config2_TU=0 -CP0_Config3=0 -CP0_Config3_DSPP=false -CP0_Config3_LPA=false -CP0_Config3_M=false -CP0_Config3_MT=false -CP0_Config3_SM=false -CP0_Config3_SP=false -CP0_Config3_TL=false -CP0_Config3_VEIC=false -CP0_Config3_VInt=false -CP0_Config_AR=0 -CP0_Config_AT=0 -CP0_Config_BE=0 -CP0_Config_MT=0 -CP0_Config_VI=0 -CP0_EBase_CPUNum=0 -CP0_IntCtl_IPPCI=0 -CP0_IntCtl_IPTI=0 -CP0_PRId=0 -CP0_PRId_CompanyID=0 -CP0_PRId_CompanyOptions=0 -CP0_PRId_ProcessorID=1 -CP0_PRId_Revision=0 -CP0_PerfCtr_M=false -CP0_PerfCtr_W=false -CP0_SrsCtl_HSS=0 -CP0_WatchHi_M=false checker=Null clock=500 cpu_id=0 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index 931c89646..8a1b8f67f 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:55:51 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:01 -M5 executing on burrito +M5 compiled Apr 19 2011 12:18:54 +M5 started Apr 19 2011 12:18:58 +M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index d5304c4b4..4243ca997 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106820 # Simulator instruction rate (inst/s) -host_mem_usage 216064 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 53148750 # Simulator tick rate (ticks/s) +host_inst_rate 798153 # Simulator instruction rate (inst/s) +host_mem_usage 195780 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 390049435 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -47,6 +47,6 @@ system.cpu.num_int_register_writes 3409 # nu system.cpu.num_load_insts 1164 # Number of load instructions system.cpu.num_mem_refs 2090 # number of memory refs system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.workload.num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 15d83d7b2..39758d41d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -21,60 +21,6 @@ work_item_id=-1 [system.cpu] type=TimingSimpleCPU children=dtb itb tracer workload -CP0_Config=0 -CP0_Config1=0 -CP0_Config1_C2=false -CP0_Config1_CA=false -CP0_Config1_DA=0 -CP0_Config1_DL=0 -CP0_Config1_DS=0 -CP0_Config1_EP=false -CP0_Config1_FP=false -CP0_Config1_IA=0 -CP0_Config1_IL=0 -CP0_Config1_IS=0 -CP0_Config1_M=0 -CP0_Config1_MD=false -CP0_Config1_MMU=0 -CP0_Config1_PC=false -CP0_Config1_WR=false -CP0_Config2=0 -CP0_Config2_M=false -CP0_Config2_SA=0 -CP0_Config2_SL=0 -CP0_Config2_SS=0 -CP0_Config2_SU=0 -CP0_Config2_TA=0 -CP0_Config2_TL=0 -CP0_Config2_TS=0 -CP0_Config2_TU=0 -CP0_Config3=0 -CP0_Config3_DSPP=false -CP0_Config3_LPA=false -CP0_Config3_M=false -CP0_Config3_MT=false -CP0_Config3_SM=false -CP0_Config3_SP=false -CP0_Config3_TL=false -CP0_Config3_VEIC=false -CP0_Config3_VInt=false -CP0_Config_AR=0 -CP0_Config_AT=0 -CP0_Config_BE=0 -CP0_Config_MT=0 -CP0_Config_VI=0 -CP0_EBase_CPUNum=0 -CP0_IntCtl_IPPCI=0 -CP0_IntCtl_IPTI=0 -CP0_PRId=0 -CP0_PRId_CompanyID=0 -CP0_PRId_CompanyOptions=0 -CP0_PRId_ProcessorID=1 -CP0_PRId_Revision=0 -CP0_PerfCtr_M=false -CP0_PerfCtr_W=false -CP0_SrsCtl_HSS=0 -CP0_WatchHi_M=false checker=Null clock=1 cpu_id=0 @@ -214,6 +160,7 @@ deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.dcache max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout index 4a1640a47..e7dec82e9 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:55:51 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:00 -M5 executing on burrito +M5 compiled Apr 19 2011 12:18:54 +M5 started Apr 19 2011 12:18:57 +M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 0a46cd560..12dfdb011 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 24226 # Simulator instruction rate (inst/s) -host_mem_usage 234168 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 1216878 # Simulator tick rate (ticks/s) +host_inst_rate 81519 # Simulator instruction rate (inst/s) +host_mem_usage 213976 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 4090793 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000293 # Number of seconds simulated @@ -47,6 +47,6 @@ system.cpu.num_int_register_writes 3409 # nu system.cpu.num_load_insts 1164 # Number of load instructions system.cpu.num_mem_refs 2090 # number of memory refs system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.workload.num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 01d13de53..00709865b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -21,60 +21,6 @@ work_item_id=-1 [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload -CP0_Config=0 -CP0_Config1=0 -CP0_Config1_C2=false -CP0_Config1_CA=false -CP0_Config1_DA=0 -CP0_Config1_DL=0 -CP0_Config1_DS=0 -CP0_Config1_EP=false -CP0_Config1_FP=false -CP0_Config1_IA=0 -CP0_Config1_IL=0 -CP0_Config1_IS=0 -CP0_Config1_M=0 -CP0_Config1_MD=false -CP0_Config1_MMU=0 -CP0_Config1_PC=false -CP0_Config1_WR=false -CP0_Config2=0 -CP0_Config2_M=false -CP0_Config2_SA=0 -CP0_Config2_SL=0 -CP0_Config2_SS=0 -CP0_Config2_SU=0 -CP0_Config2_TA=0 -CP0_Config2_TL=0 -CP0_Config2_TS=0 -CP0_Config2_TU=0 -CP0_Config3=0 -CP0_Config3_DSPP=false -CP0_Config3_LPA=false -CP0_Config3_M=false -CP0_Config3_MT=false -CP0_Config3_SM=false -CP0_Config3_SP=false -CP0_Config3_TL=false -CP0_Config3_VEIC=false -CP0_Config3_VInt=false -CP0_Config_AR=0 -CP0_Config_AT=0 -CP0_Config_BE=0 -CP0_Config_MT=0 -CP0_Config_VI=0 -CP0_EBase_CPUNum=0 -CP0_IntCtl_IPPCI=0 -CP0_IntCtl_IPTI=0 -CP0_PRId=0 -CP0_PRId_CompanyID=0 -CP0_PRId_CompanyOptions=0 -CP0_PRId_ProcessorID=1 -CP0_PRId_Revision=0 -CP0_PerfCtr_M=false -CP0_PerfCtr_W=false -CP0_SrsCtl_HSS=0 -CP0_WatchHi_M=false checker=Null clock=500 cpu_id=0 @@ -105,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -140,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -175,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 4a897b2a2..3a1be45f5 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:55:51 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:00 -M5 executing on burrito +M5 compiled Apr 19 2011 12:18:54 +M5 started Apr 19 2011 12:18:57 +M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index 27b53a7ab..ec5ae032f 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 344481 # Simulator instruction rate (inst/s) -host_mem_usage 223780 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1868884758 # Simulator tick rate (ticks/s) +host_inst_rate 524923 # Simulator instruction rate (inst/s) +host_mem_usage 203516 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2843944401 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 138 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021352 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 303 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.064694 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency @@ -188,8 +188,8 @@ system.cpu.l2cache.demand_mshr_misses 439 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005739 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -231,6 +231,6 @@ system.cpu.num_int_register_writes 3409 # nu system.cpu.num_load_insts 1164 # Number of load instructions system.cpu.num_mem_refs 2090 # number of memory refs system.cpu.num_store_insts 926 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.workload.num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- |