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| author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
| commit | 279f179babc9e5663156777c533c06edc91bce9a (patch) | |
| tree | e6718ee514cc81678491b50562ce8c463c0b20fd /tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt | |
| parent | 5aa104e072eb20f6aca49b169521b0c2da33c844 (diff) | |
| parent | 295516a590b6e47c9a881f193027447e500c749c (diff) | |
| download | gem5-279f179babc9e5663156777c533c06edc91bce9a.tar.xz | |
merge
Diffstat (limited to 'tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..325ee615a --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 259216 # Simulator instruction rate (inst/s) +host_mem_usage 263696 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 128114508 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5801 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2900000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5801 # number of cpu cycles simulated +system.cpu.num_insts 5801 # Number of instructions executed +system.cpu.num_refs 2008 # Number of memory references +system.cpu.workload.PROG:num_syscalls 9 # Number of system calls + +---------- End Simulation Statistics ---------- |