stats: update stats for the changes I pushed re: shared cache occupancy

8 files changed, 28 insertions, 19 deletions

diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
index 6b0ea33cd..508240960 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
@@ -110,6 +110,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,6 +282,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -315,6 +317,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -356,7 +359,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/power/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
index a2692a6c9..4c710c177 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 13202840. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
index bc2c673ec..85fc6bc9f 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 15 2009 15:43:13
-M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip
-M5 started Oct 15 2009 15:49:09
-M5 executing on frontend01
+M5 compiled Feb 24 2010 23:13:07
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
index 59c9aa334..4d658aa1d 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 103409                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 271924                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              212174700                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  51828                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 189300                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
+host_tick_rate                              106468871                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5800                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses              121                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.016127                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             66.056188                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses               2482                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 33461.363636                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339                       # average overall mshr miss latency
@@ -192,6 +194,8 @@ system.cpu.icache.demand_mshr_misses              330                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.077734                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            159.198376                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses               1463                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36616.094987                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121                       # average overall mshr miss latency
@@ -373,6 +377,8 @@ system.cpu.l2cache.demand_mshr_misses             426                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.005513                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           180.652204                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses               434                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34374.413146                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681                       # average overall mshr miss latency
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
index 129c166c3..930fa65ed 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -58,7 +58,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/power/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
index a2692a6c9..a2a4d88c2 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
index 410d89b19..23b972156 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 15 2009 15:43:13
-M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip
-M5 started Oct 15 2009 15:49:56
-M5 executing on frontend01
+M5 compiled Feb 24 2010 23:13:07
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
index 325ee615a..8c0754d0c 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 259216                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 263696                       # Number of bytes of host memory used
+host_inst_rate                                 277162                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 181156                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              128114508                       # Simulator tick rate (ticks/s)
+host_tick_rate                              136566988                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5801                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated