tests: Update O3 ref outputs to reflect Lisa's dist format change.

3 files changed, 34 insertions, 32 deletions

diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
index 3ef273e4f..91e0a0356 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 15924344. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 17982776. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
index 9691f5f7c..b9932c144 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simout
+Redirecting stderr to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 12 2010 02:43:42
-M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip
-M5 started May 12 2010 02:43:45
+M5 compiled Jun  6 2010 03:59:10
+M5 revision ba1a0193c050 7448 default tip
+M5 started Jun  6 2010 03:59:12
 M5 executing on zizzer
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
index 1e1223443..e78679f83 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  50476                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202684                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                              102996710                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  82571                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202992                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                              168278845                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5800                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples        10785
 system.cpu.commit.COM:committed_per_cycle::mean     0.537784                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::stdev     1.251292                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0-1         8225     76.26%     76.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1-2         1129     10.47%     86.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2-3          673      6.24%     92.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3-4          258      2.39%     95.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4-5          226      2.10%     97.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5-6          120      1.11%     98.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6-7           82      0.76%     99.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7-8           21      0.19%     99.53% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0         8225     76.26%     76.26% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1         1129     10.47%     86.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2          673      6.24%     92.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3          258      2.39%     95.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4          226      2.10%     97.46% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5          120      1.11%     98.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6           82      0.76%     99.33% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7           21      0.19%     99.53% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::8           51      0.47%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
@@ -148,14 +148,14 @@ system.cpu.fetch.rateDist::samples              11355                       # Nu
 system.cpu.fetch.rateDist::mean              1.029238                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::stdev             2.423250                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0-1                   9285     81.77%     81.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1-2                    161      1.42%     83.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2-3                    189      1.66%     84.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3-4                    155      1.37%     86.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4-5                    202      1.78%     88.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5-6                    136      1.20%     89.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6-7                    272      2.40%     91.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7-8                     77      0.68%     92.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9285     81.77%     81.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      161      1.42%     83.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      189      1.66%     84.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      155      1.37%     86.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      202      1.78%     88.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      136      1.20%     89.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      272      2.40%     91.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       77      0.68%     92.27% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::8                      878      7.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
@@ -297,14 +297,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples        11355
 system.cpu.iq.ISSUE:issued_per_cycle::mean     0.712373                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.391316                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0-1         8066     71.03%     71.03% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1-2         1182     10.41%     81.44% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2-3          820      7.22%     88.67% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3-4          507      4.46%     93.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4-5          388      3.42%     96.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5-6          218      1.92%     98.47% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6-7          121      1.07%     99.53% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7-8           46      0.41%     99.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0          8066     71.03%     71.03% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1          1182     10.41%     81.44% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2           820      7.22%     88.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3           507      4.46%     93.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4           388      3.42%     96.55% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5           218      1.92%     98.47% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6           121      1.07%     99.53% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7            46      0.41%     99.94% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::8             7      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle