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authorGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:13 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:13 -0800
commit0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch)
tree96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/quick/00.hello/ref/sparc/linux/simple-timing
parent1b64bfa933745294667158d0ce22180780b2a22e (diff)
downloadgem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz
Stats: Re update stats.
Diffstat (limited to 'tests/quick/00.hello/ref/sparc/linux/simple-timing')
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing/simout12
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt26
3 files changed, 36 insertions, 13 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 35f8386c3..d416eae87 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 9b5f99faf..1b1015662 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:05:08
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
+M5 compiled Feb 7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 02:14:00
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 28206000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 49d0076df..d21947f29 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 369934 # Simulator instruction rate (inst/s)
-host_mem_usage 207380 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 1923223783 # Simulator tick rate (ticks/s)
+host_inst_rate 87383 # Simulator instruction rate (inst/s)
+host_mem_usage 223480 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 459485360 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000028 # Number of seconds simulated
@@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 56412 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 56412 # Number of busy cycles
+system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5340 # Number of instructions executed
-system.cpu.num_refs 1402 # Number of memory references
+system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
+system.cpu.num_int_insts 4517 # number of integer instructions
+system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
+system.cpu.num_load_insts 724 # Number of load instructions
+system.cpu.num_mem_refs 1402 # number of memory refs
+system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------