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authorGabe Black <gblack@eecs.umich.edu>2006-10-27 02:21:09 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-27 02:21:09 -0400
commitca34c62bf96b66fdb1aefc3b08cad8d969ee6bc9 (patch)
tree31dcfa206871cb5f053851ea251a7e2d3e50b8c7 /tests/quick/00.hello/ref/sparc/linux/simple-timing
parent709d50cd6bb4571b13385eed578f419bef3d579c (diff)
downloadgem5-ca34c62bf96b66fdb1aefc3b08cad8d969ee6bc9.tar.xz
Update stats for fill/spill handlers
--HG-- extra : convert_revision : 2ed2e868ccbb3316f84ea691497d2e0dd4ec2416
Diffstat (limited to 'tests/quick/00.hello/ref/sparc/linux/simple-timing')
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini1
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt232
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout8
3 files changed, 120 insertions, 121 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 982973385..da87d03a1 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -20,7 +20,6 @@ print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
-print_reg_delta=false
print_thread=true
speculative=true
trace_system=client
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
index c4dc22855..3645207b1 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,67 +1,67 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 53689 # Simulator instruction rate (inst/s)
-host_mem_usage 177104 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 17808084 # Simulator tick rate (ticks/s)
+host_inst_rate 48159 # Simulator instruction rate (inst/s)
+host_mem_usage 179620 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 15510230 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 4483 # Number of instructions simulated
-sim_seconds 0.000001 # Number of seconds simulated
-sim_ticks 1497001 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 464 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3972.166667 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2972.166667 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 410 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 214497 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.116379 # miss rate for ReadReq accesses
+sim_insts 4863 # Number of instructions simulated
+sim_seconds 0.000002 # Number of seconds simulated
+sim_ticks 1573001 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3971.370370 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2971.370370 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 214454 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 160497 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.116379 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency 160454 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 501 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3980.840580 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2980.840580 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 432 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 274678 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.137725 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 69 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 205678 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.137725 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 69 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3981.559524 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2981.559524 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 334451 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 250451 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 6.845528 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 8.195652 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 965 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3977.032520 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 842 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 489175 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.127461 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3977.572464 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 548905 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 366175 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.127461 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 123 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 410905 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 965 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3977.032520 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 842 # number of overall hits
-system.cpu.dcache.overall_miss_latency 489175 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.127461 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 123 # number of overall misses
+system.cpu.dcache.overall_hits 1131 # number of overall hits
+system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 138 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 366175 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.127461 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 123 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 410905 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -74,56 +74,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 123 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 71.370810 # Cycle average of tags in use
-system.cpu.dcache.total_refs 842 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 81.997528 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_accesses 4484 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3979.178571 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.178571 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 4232 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1002753 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.056200 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 252 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 750753 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.056200 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 252 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3977.960938 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.960938 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1018358 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 762358 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 16.793651 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 4484 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3979.178571 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency
-system.cpu.icache.demand_hits 4232 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1002753 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.056200 # miss rate for demand accesses
-system.cpu.icache.demand_misses 252 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3977.960938 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
+system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1018358 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
+system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 750753 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.056200 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 252 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 762358 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 4484 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3979.178571 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 4232 # number of overall hits
-system.cpu.icache.overall_miss_latency 1002753 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.056200 # miss rate for overall accesses
-system.cpu.icache.overall_misses 252 # number of overall misses
+system.cpu.icache.overall_hits 4608 # number of overall hits
+system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
+system.cpu.icache.overall_misses 256 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 750753 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.056200 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 252 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 762358 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -136,57 +136,57 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 252 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 115.914677 # Cycle average of tags in use
-system.cpu.icache.total_refs 4232 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 114.778311 # Cycle average of tags in use
+system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 375 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2986.473118 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1985.473118 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses 394 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1110968 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.992000 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 372 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 738596 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992000 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.992386 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992386 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.008065 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.007673 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 375 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2986.473118 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1110968 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 372 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 738596 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 375 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2986.473118 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 3 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1110968 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 372 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 391 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 738596 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 372 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -199,16 +199,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 372 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 185.896040 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1497001 # number of cpu cycles simulated
-system.cpu.num_insts 4483 # Number of instructions executed
-system.cpu.num_refs 965 # Number of memory references
+system.cpu.numCycles 1573001 # number of cpu cycles simulated
+system.cpu.num_insts 4863 # Number of instructions executed
+system.cpu.num_refs 1269 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
index 3c17ee40b..b1da2e4ab 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 23 2006 07:47:36
-M5 started Mon Oct 23 07:47:41 2006
-M5 executing on zeep
+M5 compiled Oct 27 2006 02:07:29
+M5 started Fri Oct 27 02:08:11 2006
+M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
-Exiting @ tick 1497001 because target called exit()
+Exiting @ tick 1573001 because target called exit()