stats: update stats for the changes I pushed re: shared cache occupancy

3 files changed, 18 insertions, 12 deletions

diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 928e1a6a9..8f9e543cc 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 788a84f52..9485c1bb2 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:52
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:37:59
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 2f90cc999..11fb745f1 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 165633                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203084                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                              893371492                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 462498                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 190336                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                             2452978454                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000029                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses              150                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.020107                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             82.357482                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses               1389                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        55720                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        52720                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses              257                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.057478                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            117.715481                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses               5384                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55673.151751                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751                       # average overall mshr miss latency
@@ -175,6 +179,8 @@ system.cpu.l2cache.demand_mshr_misses             389                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.004176                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           136.844792                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses               392                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency