stats: update stats for preceding coherence changes

Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.

3 files changed, 51 insertions, 58 deletions

diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index d91ebcc59..35f8386c3 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 9485c1bb2..9b5f99faf 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:37:59
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:05:08
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 29031000 because target called exit()
+Hello World!Exiting @ tick 28206000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 11fb745f1..49d0076df 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 462498                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190336                       # Number of bytes of host memory used
+host_inst_rate                                 369934                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207380                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2452978454                       # Simulator tick rate (ticks/s)
+host_tick_rate                             1923223783                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
-sim_seconds                                  0.000029                       # Number of seconds simulated
-sim_ticks                                    29031000                       # Number of ticks simulated
+sim_seconds                                  0.000028                       # Number of seconds simulated
+sim_ticks                                    28206000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses                716                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222                       # average ReadReq mshr miss latency
@@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses              54                       # nu
 system.cpu.dcache.WriteReq_accesses               673                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   577                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       5376000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.142645                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                  96                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      5088000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.142645                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             96                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits                   592                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency       4536000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.120357                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                  81                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency      4293000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.120357                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses             81                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                   9.288889                       # Average number of references to valid blocks.
@@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                1389                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency        55720                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        52720                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    1239                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         8358000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.107991                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   150                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 55688.888889                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                    1254                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         7518000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.097192                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   135                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      7908000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.107991                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              150                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency      7113000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.097192                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              135                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.020107                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0             82.357482                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.020036                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             82.065697                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses               1389                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency        55720                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        52720                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55688.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   1239                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        8358000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.107991                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  150                       # number of overall misses
+system.cpu.dcache.overall_hits                   1254                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        7518000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.097192                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  135                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      7908000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.107991                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             150                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency      7113000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.097192                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             135                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 82.357482                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 82.065697                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1254                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              257                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.057478                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            117.715481                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.057117                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            116.975932                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses               5384                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55673.151751                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751                       # average overall mshr miss latency
@@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    257                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                117.715481                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                116.975932                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5127                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -148,18 +148,9 @@ system.cpu.l2cache.ReadReq_misses                 308                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency     12320000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.990354                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            308                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             15                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency       780000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               15                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       600000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           15                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.010239                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.009740                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -179,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses             389                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.004176                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           136.844792                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.004337                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           142.102892                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses               392                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -196,14 +187,14 @@ system.cpu.l2cache.overall_mshr_misses            389                       # nu
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   293                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   308                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               136.844792                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               142.102892                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            58062                       # number of cpu cycles simulated
+system.cpu.numCycles                            56412                       # number of cpu cycles simulated
 system.cpu.num_insts                             5340                       # Number of instructions executed
 system.cpu.num_refs                              1402                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls