diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
| commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
| tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /tests/quick/00.hello/ref/sparc | |
| parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
| parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
| download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz | |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'tests/quick/00.hello/ref/sparc')
12 files changed, 187 insertions, 202 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 73da00d73..970388ae5 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..eefaf1737 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py quick/00.hello/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 9a9ac5a12..b09b910ba 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1230 # Simulator instruction rate (inst/s) -host_mem_usage 173824 # Number of bytes of host memory used -host_seconds 3.93 # Real time elapsed on the host -host_tick_rate 622698 # Simulator tick rate (ticks/s) +host_inst_rate 25851 # Simulator instruction rate (inst/s) +host_mem_usage 193720 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 13060676 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2447500 # Number of ticks simulated +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2701000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4896 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index 41aec2f86..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7012 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout deleted file mode 100644 index cf86d0964..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,13 +0,0 @@ -Hello World!M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2447500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index ef40ce3fd..f68b9582f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..fcae28521 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py quick/00.hello/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 08e810a08..cf7518d98 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,232 +1,205 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153074 # Simulator instruction rate (inst/s) -host_mem_usage 195092 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 524572616 # Simulator tick rate (ticks/s) +host_inst_rate 21374 # Simulator instruction rate (inst/s) +host_mem_usage 201092 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 116036277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16662000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29031000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 565 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.145234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.145234 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.400000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1119 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118203 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.118203 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1119 # number of overall hits -system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118203 # miss rate for overall accesses +system.cpu.dcache.overall_hits 1239 # number of overall hits +system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.118203 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.706581 # Cycle average of tags in use -system.cpu.dcache.total_refs 1134 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use +system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.437500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.437500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6886000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency -system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6886000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses -system.cpu.icache.demand_misses 256 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency +system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4621 # number of overall hits -system.cpu.icache.overall_miss_latency 6886000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses -system.cpu.icache.overall_misses 256 # number of overall misses +system.cpu.icache.overall_hits 5127 # number of overall hits +system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6118000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.043041 # Cycle average of tags in use -system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use +system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7061000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992327 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 388 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4268000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992327 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 388 # number of overall misses +system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4268000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.841445 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 33324 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 58062 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index 2a6ac4135..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout deleted file mode 100644 index 12e9a5d09..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,13 +0,0 @@ -Hello World!M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Sun Feb 24 13:28:47 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 16662000 because target called exit() |