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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-05-11 10:38:46 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-05-11 10:38:46 -0700 |
commit | b174ec065e2b9f8ffa68c350b2563819eef5e9b1 (patch) | |
tree | 247eaf664b887559a1575d0733daa2179741bcd2 /tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr | |
parent | 6df61e1f2409e336dc4ae68eaeae7d0638e65a9d (diff) | |
download | gem5-b174ec065e2b9f8ffa68c350b2563819eef5e9b1.tar.xz |
ruby: Initial references for ruby regressions
Diffstat (limited to 'tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr')
-rwxr-xr-x | tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here |