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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-06 22:14:23 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-06 22:14:23 -0800
commit45f881919fc9c4d2b2d4ea9f165fb567aad9849a (patch)
tree2a6ebbec93e62ef5279ec35e27e06f86577372fd /tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
parentf5aa75fdc528aca122ac1369fa4ac3df8a915027 (diff)
downloadgem5-45f881919fc9c4d2b2d4ea9f165fb567aad9849a.tar.xz
regress: Regression Tester output updates
Diffstat (limited to 'tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt')
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt26
1 files changed, 21 insertions, 5 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index 519e51040..db1eee29b 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 101671 # Simulator instruction rate (inst/s)
-host_mem_usage 223168 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
-host_tick_rate 297579540 # Simulator tick rate (ticks/s)
+host_inst_rate 650703 # Simulator instruction rate (inst/s)
+host_mem_usage 207316 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1875725370 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
@@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 57536 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 57536 # Number of busy cycles
+system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 9810 # Number of instructions executed
-system.cpu.num_refs 1990 # Number of memory references
+system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
+system.cpu.num_int_insts 9715 # number of integer instructions
+system.cpu.num_int_register_reads 26194 # number of times the integer registers were read
+system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
+system.cpu.num_load_insts 1056 # Number of load instructions
+system.cpu.num_mem_refs 1990 # number of memory refs
+system.cpu.num_store_insts 934 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------