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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
| commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
| tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/quick/00.hello/ref/x86/linux | |
| parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
| download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz | |
Stats: Re update stats.
Diffstat (limited to 'tests/quick/00.hello/ref/x86/linux')
13 files changed, 158 insertions, 57 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index 202d0b795..1fab00bfb 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 12f04436f..0767b9777 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 0a112c922..182e72d25 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48300 # Simulator instruction rate (inst/s) -host_mem_usage 226820 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 67673766 # Simulator tick rate (ticks/s) +host_inst_rate 47133 # Simulator instruction rate (inst/s) +host_mem_usage 227692 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 66053082 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed +system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 9714 # Number of committed integer instructions. system.cpu.commit.COM:loads 1056 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1990 # Number of memory references committed @@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency @@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 304 # system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 25083 # number of integer regfile reads +system.cpu.int_regfile_writes 11189 # number of integer regfile writes system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued @@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate +system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ @@ -414,7 +428,10 @@ system.cpu.memDep0.conflictingLoads 4 # Nu system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 5334 # number of misc regfile reads system.cpu.numCycles 27533 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full @@ -427,10 +444,14 @@ system.cpu.rename.RENAME:RunCycles 8027 # Nu system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 28728 # The number of ROB reads +system.cpu.rob.rob_writes 28005 # The number of ROB writes system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index f4bc2655d..ee37f754f 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 0a2d88a32..09f4d0b50 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 7219cd6a7..1dca11ec5 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 137874 # Simulator instruction rate (inst/s) -host_mem_usage 215488 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 79078853 # Simulator tick rate (ticks/s) +host_inst_rate 180423 # Simulator instruction rate (inst/s) +host_mem_usage 219128 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 103433649 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 5651000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11303 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 11303 # Number of busy cycles +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_refs 1990 # Number of memory references +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_store_insts 934 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 5985e429a..a51884b7a 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -10,6 +10,13 @@ type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -147,6 +154,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer children=dcache +access_phys_mem=true dcache=system.ruby.cpu_ruby_ports.dcache deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.dcache diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index adfa92f7c..a12716c02 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/04/2011 03:47:05 +Real time: Feb/07/2011 02:32:13 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.19 -Virtual_time_in_minutes: 0.00316667 -Virtual_time_in_hours: 5.27778e-05 -Virtual_time_in_days: 2.19907e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 38.8594 -mbytes_total: 233.992 -resident_ratio: 0.166088 +mbytes_resident: 38.6094 +mbytes_total: 231.508 +resident_ratio: 0.16679 ruby_cycles_executed: [ 276485 ] @@ -71,8 +71,9 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average: 3 | standard deviation: 0 | 0 0 0 7523 ] miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -87,10 +88,12 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 ave imcomplete_dir_Times: 1376 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average: 3 | standard deviation: 0 | 0 0 0 6287 ] miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 556 average: 3 | standard deviation: 0 | 0 0 0 556 ] -miss_latency_LD_Directory: [binsize: 2 max: 293 count: 500 average: 178.96 | standard deviation: 22.8334 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average: 3 | standard deviation: 0 | 0 0 0 549 ] +miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ] miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] +miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -122,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11021 +page_reclaims: 10950 page_faults: 0 swaps: 0 block_inputs: 0 @@ -177,17 +180,17 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.3108% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.4459% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185% system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433% system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1377 100% --- L1Cache --- - Event Counts - -Load [1056 ] 1056 +Load [1048 ] 1048 Ifetch [6910 ] 6910 -Store [934 ] 934 +Store [942 ] 942 Data [1377 ] 1377 Fwd_GETX [0 ] 0 Inv [0 ] 0 @@ -196,17 +199,17 @@ Writeback_Ack [1373 ] 1373 Writeback_Nack [0 ] 0 - Transitions - -I Load [500 ] 500 +I Load [499 ] 499 I Ifetch [623 ] 623 -I Store [254 ] 254 +I Store [255 ] 255 I Inv [0 ] 0 I Replacement [0 ] 0 II Writeback_Nack [0 ] 0 -M Load [556 ] 556 +M Load [549 ] 549 M Ifetch [6287 ] 6287 -M Store [680 ] 680 +M Store [687 ] 687 M Fwd_GETX [0 ] 0 M Inv [0 ] 0 M Replacement [1373 ] 1373 @@ -218,9 +221,9 @@ MI Writeback_Nack [0 ] 0 MII Fwd_GETX [0 ] 0 -IS Data [1123 ] 1123 +IS Data [1122 ] 1122 -IM Data [254 ] 254 +IM Data [255 ] 255 Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2750 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 4e5806bd6..877c8d9b9 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 4 2011 03:47:02 -M5 revision afcc4492291f 7892 default qbase qtip rubystatupdate.patch tip -M5 started Feb 4 2011 03:47:05 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 806c6c56a..b88df01c5 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106685 # Simulator instruction rate (inst/s) -host_mem_usage 239612 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 3002497 # Simulator tick rate (ticks/s) +host_inst_rate 32378 # Simulator instruction rate (inst/s) +host_mem_usage 237068 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 911908 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 276484 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 276484 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 276484 # Number of busy cycles +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_refs 1990 # Number of memory references +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_store_insts 934 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index 9743aff19..ab79b8cce 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index d7b40c980..d6afbecf0 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:24 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 519e51040..0c21882f5 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 101671 # Simulator instruction rate (inst/s) -host_mem_usage 223168 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 297579540 # Simulator tick rate (ticks/s) +host_inst_rate 594010 # Simulator instruction rate (inst/s) +host_mem_usage 226844 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1712507148 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 57536 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 57536 # Number of busy cycles +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_refs 1990 # Number of memory references +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_store_insts 934 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- |