diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:11 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:11 -0800 |
| commit | 1b64bfa933745294667158d0ce22180780b2a22e (patch) | |
| tree | 11822ba69a5ec4c1c4b7ad72fcf08c87e143e4fe /tests/quick/00.hello/ref/x86 | |
| parent | 44e5e7e0533ba2544f2d37f8e051a0422966bd9b (diff) | |
| download | gem5-1b64bfa933745294667158d0ce22180780b2a22e.tar.xz | |
Stats: Back out broken update.
Diffstat (limited to 'tests/quick/00.hello/ref/x86')
13 files changed, 509 insertions, 143 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr index 562787dcb..94d399eab 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr @@ -1,9 +1,7 @@ -Traceback (most recent call last): - File "<string>", line 1, in <module> - File "/proj/radl_extra/users/bbeckman/noc_m5/src/python/m5/main.py", line 359, in main - exec filecode in scope - File "tests/run.py", line 70, in <module> - execfile(joinpath(tests_root, 'configs', test_filename + '.py')) - File "tests/configs/o3-timing.py", line 40, in <module> - cpu = DerivO3CPU(cpu_id=0) -NameError: name 'DerivO3CPU' is not defined +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 781dde786..12f04436f 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,8 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 15:49:25 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 15:49:33 -M5 executing on svnxelk05 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing +M5 compiled Jan 31 2011 16:34:44 +M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch +M5 started Jan 31 2011 16:34:46 +M5 executing on burrito +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 13766000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index e69de29bb..0a112c922 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -0,0 +1,437 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 48300 # Simulator instruction rate (inst/s) +host_mem_usage 226820 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 67673766 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 9809 # Number of instructions simulated +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13766000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1892 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1920 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 1920 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 1214 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 37 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle::samples 15124 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.648572 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.100130 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 9612 63.55% 63.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 3088 20.42% 83.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1220 8.07% 92.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 836 5.53% 97.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 232 1.53% 99.10% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 57 0.38% 99.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 30 0.20% 99.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 12 0.08% 99.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 37 0.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle +system.cpu.commit.COM:count 9809 # Number of instructions committed +system.cpu.commit.COM:loads 1056 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1990 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 3832 # The number of squashed insts skipped by commit +system.cpu.committedInsts 9809 # Number of Instructions Simulated +system.cpu.committedInsts_total 9809 # Number of Instructions Simulated +system.cpu.cpi 2.806912 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.806912 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1244 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1168 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2820000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.061093 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 76 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2173000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.049839 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 62 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2790500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 12.870504 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2178 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33913.881748 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1789 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 13192500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.178604 # miss rate for demand accesses +system.cpu.dcache.demand_misses 389 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 249 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4963500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.064279 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.020744 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 84.965644 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2178 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33913.881748 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1789 # number of overall hits +system.cpu.dcache.overall_miss_latency 13192500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.178604 # miss rate for overall accesses +system.cpu.dcache.overall_misses 389 # number of overall misses +system.cpu.dcache.overall_mshr_hits 249 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4963500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.064279 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 139 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 84.965644 # Cycle average of tags in use +system.cpu.dcache.total_refs 1789 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 464 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 15304 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6233 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 8371 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 721 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 56 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1920 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1255 # Number of cache lines fetched +system.cpu.fetch.Cycles 9031 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 8830 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.069735 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1255 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.320706 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002083 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.178869 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 7129 44.99% 44.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4489 28.33% 73.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1878 11.85% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2046 12.91% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 57 0.36% 98.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 227 1.43% 99.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 970 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 10664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.227092 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 285 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 9040500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.205578 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 258 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.759690 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1255 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 37417.543860 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency +system.cpu.icache.demand_hits 970 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 10664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.227092 # miss rate for demand accesses +system.cpu.icache.demand_misses 285 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 9040500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.205578 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 258 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.061525 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 126.002915 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1255 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 37417.543860 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 970 # number of overall hits +system.cpu.icache.overall_miss_latency 10664000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.227092 # miss rate for overall accesses +system.cpu.icache.overall_misses 285 # number of overall misses +system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 9040500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.205578 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 258 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 258 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 126.002915 # Cycle average of tags in use +system.cpu.icache.total_refs 970 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 11688 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1318 # Number of branches executed +system.cpu.iew.EXEC:nop 0 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.434678 # Inst execution rate +system.cpu.iew.EXEC:refs 2353 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1060 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 10358 # num instructions consuming a value +system.cpu.iew.WB:count 11818 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.702935 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 7281 # num instructions producing a value +system.cpu.iew.WB:rate 0.429230 # insts written-back per cycle +system.cpu.iew.WB:sent 11866 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 487 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 58 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1535 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 418 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1238 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 13635 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1293 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 536 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 11968 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 21 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 479 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 304 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 10018 80.12% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1360 10.88% 91.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1123 8.98% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 12504 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.000320 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3 75.00% 75.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1 25.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 15845 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.789145 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.977935 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8160 51.50% 51.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 4079 25.74% 77.24% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 2594 16.37% 93.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 834 5.26% 98.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 157 0.99% 99.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 19 0.12% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 2 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate +system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3342 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5066 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2690500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2443500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 320 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 10872000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.993750 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 318 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9859500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993750 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 318 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.006309 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 398 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34248.737374 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.994975 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 396 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 12303000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.994975 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.004816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 157.820330 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34248.737374 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.994975 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 396 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 12303000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.994975 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 317 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 157.820330 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 27533 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 6603 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 38664 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 14745 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 13787 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 8027 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed +system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 0fc15a925..f4bc2655d 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -10,13 +10,6 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -66,7 +59,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 96e1eca08..0a2d88a32 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 15:49:25 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 20:48:09 -M5 executing on SC2B0617 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic +M5 compiled Jan 31 2011 14:03:49 +M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip +M5 started Jan 31 2011 14:03:51 +M5 executing on burrito +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index d93e7eed9..7219cd6a7 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 805088 # Simulator instruction rate (inst/s) -host_mem_usage 199588 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 453713368 # Simulator tick rate (ticks/s) +host_inst_rate 137874 # Simulator instruction rate (inst/s) +host_mem_usage 215488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 79078853 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated @@ -11,24 +11,8 @@ sim_ticks 5651000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11303 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 11303 # Number of busy cycles -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses -system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read -system.cpu.num_int_register_writes 9368 # number of times the integer registers were written -system.cpu.num_load_insts 1056 # Number of load instructions -system.cpu.num_mem_refs 1990 # number of memory refs -system.cpu.num_store_insts 934 # Number of store instructions +system.cpu.num_refs 1990 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index d0926d8e6..5985e429a 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -10,13 +10,6 @@ type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -63,7 +56,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -154,7 +147,6 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer children=dcache -access_phys_mem=true dcache=system.ruby.cpu_ruby_ports.dcache deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.dcache diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index 27560c564..adfa92f7c 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/06/2011 20:48:09 +Real time: Feb/04/2011 03:47:05 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.36 -Virtual_time_in_minutes: 0.006 -Virtual_time_in_hours: 0.0001 -Virtual_time_in_days: 4.16667e-06 +Virtual_time_in_seconds: 0.19 +Virtual_time_in_minutes: 0.00316667 +Virtual_time_in_hours: 5.27778e-05 +Virtual_time_in_days: 2.19907e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 36.707 -mbytes_total: 212.684 -resident_ratio: 0.172627 +mbytes_resident: 38.8594 +mbytes_total: 233.992 +resident_ratio: 0.166088 ruby_cycles_executed: [ 276485 ] @@ -71,9 +71,8 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average: 3 | standard deviation: 0 | 0 0 0 7523 ] miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -88,12 +87,10 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 ave imcomplete_dir_Times: 1376 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average: 3 | standard deviation: 0 | 0 0 0 6287 ] miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average: 3 | standard deviation: 0 | 0 0 0 549 ] -miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 556 average: 3 | standard deviation: 0 | 0 0 0 556 ] +miss_latency_LD_Directory: [binsize: 2 max: 293 count: 500 average: 178.96 | standard deviation: 22.8334 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ] miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] -miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -125,11 +122,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10563 +page_reclaims: 11021 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- @@ -180,17 +177,17 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.3108% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.4459% system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433% system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1377 100% --- L1Cache --- - Event Counts - -Load [1048 ] 1048 +Load [1056 ] 1056 Ifetch [6910 ] 6910 -Store [942 ] 942 +Store [934 ] 934 Data [1377 ] 1377 Fwd_GETX [0 ] 0 Inv [0 ] 0 @@ -199,17 +196,17 @@ Writeback_Ack [1373 ] 1373 Writeback_Nack [0 ] 0 - Transitions - -I Load [499 ] 499 +I Load [500 ] 500 I Ifetch [623 ] 623 -I Store [255 ] 255 +I Store [254 ] 254 I Inv [0 ] 0 I Replacement [0 ] 0 II Writeback_Nack [0 ] 0 -M Load [549 ] 549 +M Load [556 ] 556 M Ifetch [6287 ] 6287 -M Store [687 ] 687 +M Store [680 ] 680 M Fwd_GETX [0 ] 0 M Inv [0 ] 0 M Replacement [1373 ] 1373 @@ -221,9 +218,9 @@ MI Writeback_Nack [0 ] 0 MII Fwd_GETX [0 ] 0 -IS Data [1122 ] 1122 +IS Data [1123 ] 1123 -IM Data [255 ] 255 +IM Data [254 ] 254 Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2750 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 58b226717..4e5806bd6 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 15:49:25 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 20:48:09 -M5 executing on SC2B0617 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby +M5 compiled Feb 4 2011 03:47:02 +M5 revision afcc4492291f 7892 default qbase qtip rubystatupdate.patch tip +M5 started Feb 4 2011 03:47:05 +M5 executing on burrito +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 10481a15c..806c6c56a 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86745 # Simulator instruction rate (inst/s) -host_mem_usage 217792 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 2441144 # Simulator tick rate (ticks/s) +host_inst_rate 106685 # Simulator instruction rate (inst/s) +host_mem_usage 239612 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 3002497 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -11,24 +11,8 @@ sim_ticks 276484 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 276484 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 276484 # Number of busy cycles -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses -system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read -system.cpu.num_int_register_writes 9368 # number of times the integer registers were written -system.cpu.num_load_insts 1056 # Number of load instructions -system.cpu.num_mem_refs 1990 # number of memory refs -system.cpu.num_store_insts 934 # Number of store instructions +system.cpu.num_refs 1990 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index 968af204d..9743aff19 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -10,13 +10,6 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -166,7 +159,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 4427ab320..d7b40c980 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 15:49:25 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 20:48:09 -M5 executing on SC2B0617 -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing +M5 compiled Jan 31 2011 14:03:49 +M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip +M5 started Jan 31 2011 14:03:51 +M5 executing on burrito +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index db1eee29b..519e51040 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 650703 # Simulator instruction rate (inst/s) -host_mem_usage 207316 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1875725370 # Simulator tick rate (ticks/s) +host_inst_rate 101671 # Simulator instruction rate (inst/s) +host_mem_usage 223168 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 297579540 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -195,24 +195,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 57536 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 57536 # Number of busy cycles -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses -system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read -system.cpu.num_int_register_writes 9368 # number of times the integer registers were written -system.cpu.num_load_insts 1056 # Number of load instructions -system.cpu.num_mem_refs 1990 # number of memory refs -system.cpu.num_store_insts 934 # Number of store instructions +system.cpu.num_refs 1990 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- |