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authorSteve Reinhardt <stever@gmail.com>2009-02-16 12:09:45 -0500
committerSteve Reinhardt <stever@gmail.com>2009-02-16 12:09:45 -0500
commit89ea32325094665c16688212b5a2cd7b7bbf5f03 (patch)
tree2259a04ed0e6c700096d8f662726c51a2c6da525 /tests/quick/00.hello/ref/x86
parent89a7fb03934b3e38c7d8b2c4818794b3ec874fdf (diff)
downloadgem5-89ea32325094665c16688212b5a2cd7b7bbf5f03.tar.xz
Update stats for new prefetching fixes.
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
Diffstat (limited to 'tests/quick/00.hello/ref/x86')
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini3
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic/simout11
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing/simout11
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt35
8 files changed, 35 insertions, 55 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index 140ac8ef9..1a9a034e8 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
index 72ba90ece..94d399eab 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 66f32751d..5d849e6d3 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 26 2008 18:29:56
-M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
-M5 commit date Fri Dec 26 18:25:21 2008 -0800
-M5 started Dec 26 2008 18:30:07
-M5 executing on fajita
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
+M5 compiled Feb 16 2009 00:19:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:19:16
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 2ee3e5703..a5ec37276 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5132 # Simulator instruction rate (inst/s)
-host_mem_usage 192872 # Number of bytes of host memory used
-host_seconds 1.85 # Real time elapsed on the host
-host_tick_rate 2983162 # Simulator tick rate (ticks/s)
+host_inst_rate 51320 # Simulator instruction rate (inst/s)
+host_mem_usage 193224 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
+host_tick_rate 29796099 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index 6b3961ac8..d1edd6c59 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
index 72ba90ece..94d399eab 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index e9fb59225..23d83ecb3 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Dec 26 2008 18:29:56
-M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
-M5 commit date Fri Dec 26 18:25:21 2008 -0800
-M5 started Dec 26 2008 19:57:21
-M5 executing on fajita
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
+M5 compiled Feb 16 2009 00:19:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:19:16
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index 4bf18211b..58aaf6112 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 494241 # Simulator instruction rate (inst/s)
-host_mem_usage 200332 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 1743803782 # Simulator tick rate (ticks/s)
+host_inst_rate 63293 # Simulator instruction rate (inst/s)
+host_mem_usage 200624 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
+host_tick_rate 225441997 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000034 # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.076497 # ms
system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.020731 # ms
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -207,15 +189,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # m
system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions