diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/quick/00.hello/ref | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/quick/00.hello/ref')
27 files changed, 871 insertions, 864 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 03a16a5ea..d63a5e401 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index fa9debdd1..7a521752f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 20:03:54 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 20 2011 15:52:45 +gem5 started Aug 20 2011 15:52:55 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12003500 because target called exit() +Exiting @ tick 12004500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index a8b7869e5..1aa86fca4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12003500 # Number of ticks simulated +sim_ticks 12004500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47992 # Simulator instruction rate (inst/s) -host_tick_rate 90187460 # Simulator tick rate (ticks/s) -host_mem_usage 243780 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 61962 # Simulator instruction rate (inst/s) +host_tick_rate 116453376 # Simulator tick rate (ticks/s) +host_mem_usage 204272 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 1860 # DTB read hits -system.cpu.dtb.read_misses 45 # DTB read misses +system.cpu.dtb.read_misses 44 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1905 # DTB read accesses -system.cpu.dtb.write_hits 1043 # DTB write hits +system.cpu.dtb.read_accesses 1904 # DTB read accesses +system.cpu.dtb.write_hits 1041 # DTB write hits system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1071 # DTB write accesses -system.cpu.dtb.data_hits 2903 # DTB hits -system.cpu.dtb.data_misses 73 # DTB misses +system.cpu.dtb.write_accesses 1069 # DTB write accesses +system.cpu.dtb.data_hits 2901 # DTB hits +system.cpu.dtb.data_misses 72 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2976 # DTB accesses -system.cpu.itb.fetch_hits 2041 # ITB hits +system.cpu.dtb.data_accesses 2973 # DTB accesses +system.cpu.itb.fetch_hits 2039 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2070 # ITB accesses +system.cpu.itb.fetch_accesses 2068 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,177 +41,177 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24008 # number of cpu cycles simulated +system.cpu.numCycles 24010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2505 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1456 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1935 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 719 # Number of BTB hits +system.cpu.BPredUnit.lookups 2507 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1457 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 459 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 718 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14447 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1092 # Number of branches that fetch has predicted taken +system.cpu.fetch.Insts 14456 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2507 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1091 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1555 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 1556 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2041 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12591 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.147407 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.529389 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12592 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.148030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.530696 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9972 79.20% 79.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 273 2.17% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 226 1.79% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.76% 84.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 235 1.87% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 177 1.41% 88.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 258 2.05% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.12% 91.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1087 8.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9973 79.20% 79.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.18% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 224 1.78% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.76% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 234 1.86% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 178 1.41% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.04% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 140 1.11% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1090 8.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12591 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104340 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.601758 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7971 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 12592 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104415 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.602082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7970 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2448 # Number of cycles decode is running +system.cpu.decode.RunCycles 2449 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 977 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 978 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13375 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13378 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 977 # Number of cycles rename is squashing +system.cpu.rename.SquashCycles 978 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2318 # Number of cycles rename is running system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12830 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12829 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9571 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16046 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16029 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16037 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16020 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4988 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4990 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2392 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1263 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11550 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11558 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9758 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4875 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2832 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9757 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4883 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2853 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12591 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.774998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.396796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.774857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.395692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8508 67.57% 67.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1466 11.64% 79.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1070 8.50% 87.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8510 67.58% 67.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1462 11.61% 79.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1072 8.51% 87.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 438 3.48% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 253 2.01% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 440 3.49% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.02% 98.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 128 1.02% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.24% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12591 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12592 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 54 51.43% 63.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 12.26% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 54 50.94% 63.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 36.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6577 67.40% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2074 21.25% 88.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1102 11.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6575 67.39% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2074 21.26% 88.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1103 11.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9758 # Type of FU issued -system.cpu.iq.rate 0.406448 # Inst issue rate -system.cpu.iq.fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010760 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32236 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16459 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8983 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9757 # Type of FU issued +system.cpu.iq.rate 0.406372 # Inst issue rate +system.cpu.iq.fu_busy_cnt 106 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010864 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16474 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8982 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses @@ -219,63 +219,63 @@ system.cpu.iq.int_alu_accesses 9850 # Nu system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1207 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1206 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 398 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 406 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 977 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 978 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11657 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 11665 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2392 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1263 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 446 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9316 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1915 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 447 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1914 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 2988 # number of memory reference insts executed +system.cpu.iew.exec_refs 2985 # number of memory reference insts executed system.cpu.iew.exec_branches 1504 # Number of branches executed -system.cpu.iew.exec_stores 1073 # Number of stores executed -system.cpu.iew.exec_rate 0.388037 # Inst execution rate -system.cpu.iew.wb_sent 9122 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8993 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4720 # num instructions producing a value -system.cpu.iew.wb_consumers 6405 # num instructions consuming a value +system.cpu.iew.exec_stores 1071 # Number of stores executed +system.cpu.iew.exec_rate 0.387880 # Inst execution rate +system.cpu.iew.wb_sent 9119 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8992 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4719 # num instructions producing a value +system.cpu.iew.wb_consumers 6404 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374583 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736924 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374511 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5251 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.413328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.413084 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 241 2.08% 95.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 158 1.36% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 240 2.07% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 159 1.37% 96.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.39% 98.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 46 0.40% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 162 1.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle @@ -289,50 +289,50 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 162 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22754 # The number of ROB reads -system.cpu.rob.rob_writes 24296 # The number of ROB writes +system.cpu.rob.rob_reads 22763 # The number of ROB reads +system.cpu.rob.rob_writes 24313 # The number of ROB writes system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11417 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.759474 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.759474 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11838 # number of integer regfile reads +system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads +system.cpu.ipc 0.265973 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265973 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11830 # number of integer regfile reads system.cpu.int_regfile_writes 6732 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.648657 # Cycle average of tags in use -system.cpu.icache.total_refs 1609 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.173633 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 160.112304 # Cycle average of tags in use +system.cpu.icache.total_refs 1606 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 159.648657 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.077953 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1609 # number of ReadReq hits -system.cpu.icache.demand_hits 1609 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1609 # number of overall hits -system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses -system.cpu.icache.demand_misses 432 # number of demand (read+write) misses -system.cpu.icache.overall_misses 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15393500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15393500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15393500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2041 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2041 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.211661 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.211661 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.211661 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35633.101852 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35633.101852 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35633.101852 # average overall miss latency +system.cpu.icache.occ_blocks::0 160.112304 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.078180 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1606 # number of ReadReq hits +system.cpu.icache.demand_hits 1606 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1606 # number of overall hits +system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses +system.cpu.icache.demand_misses 433 # number of demand (read+write) misses +system.cpu.icache.overall_misses 433 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15431000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15431000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15431000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2039 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.212359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.212359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.212359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35637.413395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35637.413395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35637.413395 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -345,31 +345,31 @@ system.cpu.icache.writebacks 0 # nu system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10986500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10986500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10986500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11021000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.152376 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.152376 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.152376 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35326.366559 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.153016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.153016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.153016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.717949 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.288630 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.288630 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 109.290272 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits @@ -379,10 +379,10 @@ system.cpu.dcache.ReadReq_misses 154 # nu system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5497000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5497500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17964500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17964500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency 17965000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17965000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses @@ -391,10 +391,10 @@ system.cpu.dcache.ReadReq_miss_rate 0.085603 # mi system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35694.805195 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 35698.051948 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35224.509804 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35224.509804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35225.490196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35225.490196 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,54 +413,54 @@ system.cpu.dcache.WriteReq_mshr_misses 73 # nu system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3654500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6266000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36183.168317 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.178797 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.178797 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.643066 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006764 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 411 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 484 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14129000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14163000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16642500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16642500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency 16676500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16676500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 413 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997573 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997579 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34377.128954 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_rate 0.997942 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997942 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34376.213592 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34385.330579 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34385.330579 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34384.536082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34384.536082 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,24 +472,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 411 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 484 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 484 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12819000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12850000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15105000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15136000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15136000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997573 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997579 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997938 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997938 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.781022 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.997942 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997942 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.320388 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 1c3640f5b..c7e464eb4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index b62422ecd..f41676f5c 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 20:04:15 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 20 2011 15:52:45 +gem5 started Aug 20 2011 15:52:55 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 886aae88f..d7cfe3b16 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000007 # Number of seconds simulated sim_ticks 6833000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36521 # Simulator instruction rate (inst/s) -host_tick_rate 104491306 # Simulator tick rate (ticks/s) -host_mem_usage 242860 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 39761 # Simulator instruction rate (inst/s) +host_tick_rate 113766137 # Simulator tick rate (ticks/s) +host_mem_usage 203344 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 1035 # DT system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 1079 # DTB accesses -system.cpu.itb.fetch_hits 945 # ITB hits +system.cpu.itb.fetch_hits 941 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 975 # ITB accesses +system.cpu.itb.fetch_accesses 971 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -44,87 +44,87 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 13667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1041 # Number of BP lookups +system.cpu.BPredUnit.lookups 1038 # Number of BP lookups system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 733 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 220 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3751 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6413 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1041 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 430 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1115 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 754 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 945 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 157 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 941 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.004700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.420463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5268 82.53% 82.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60 0.94% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 118 1.85% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 94 1.47% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 2.19% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.91% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.86% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 1.02% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076169 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.469232 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4642 # Number of cycles decode is idle +system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1083 # Number of cycles decode is running +system.cpu.decode.RunCycles 1081 # Number of cycles decode is running system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 426 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5734 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 426 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4737 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 997 # Number of cycles rename is running +system.cpu.rename.RunCycles 995 # Number of cycles rename is running system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5480 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3945 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6160 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6148 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2177 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4659 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3882 # Number of instructions issued +system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1179 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608178 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298400 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4812 75.39% 75.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 543 8.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle @@ -171,79 +171,79 @@ system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2767 71.28% 71.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 734 18.91% 90.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3882 # Type of FU issued -system.cpu.iq.rate 0.284042 # Inst issue rate +system.cpu.iq.FU_type_0::total 3881 # Type of FU issued +system.cpu.iq.rate 0.283969 # Inst issue rate system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010562 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14224 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6793 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3916 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 426 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5003 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 133 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 338 # number of nop insts executed system.cpu.iew.exec_refs 1080 # number of memory reference insts executed @@ -259,18 +259,18 @@ system.cpu.iew.wb_rate 0.261872 # in system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 5957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.432432 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.291215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5066 85.04% 85.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 221 3.71% 88.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 314 5.27% 94.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 118 1.98% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 71 1.19% 97.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle @@ -278,7 +278,7 @@ system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 5957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 709 # Number of memory references committed @@ -290,8 +290,8 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 10644 # The number of ROB reads -system.cpu.rob.rob_writes 10417 # The number of ROB writes +system.cpu.rob.rob_reads 10645 # The number of ROB reads +system.cpu.rob.rob_writes 10410 # The number of ROB writes system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated @@ -307,27 +307,27 @@ system.cpu.misc_regfile_reads 1 # nu system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use -system.cpu.icache.total_refs 704 # Total number of references to valid blocks. +system.cpu.icache.total_refs 700 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.805405 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 704 # number of ReadReq hits -system.cpu.icache.demand_hits 704 # number of demand (read+write) hits -system.cpu.icache.overall_hits 704 # number of overall hits +system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits +system.cpu.icache.demand_hits 700 # number of demand (read+write) hits +system.cpu.icache.overall_hits 700 # number of overall hits system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses system.cpu.icache.demand_misses 241 # number of demand (read+write) misses system.cpu.icache.overall_misses 241 # number of overall misses system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 945 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 945 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 945 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.255026 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.255026 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.255026 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency @@ -351,9 +351,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.195767 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.195767 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.195767 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index b56607812..6ed416710 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 57d02de26..d350ca8e5 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 04:26:12 -gem5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 13:15:14 +gem5 executing on zizzer +command line: ./build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 6012e4873..5bb9beb5c 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000010 # Number of seconds simulated sim_ticks 9807000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35563 # Simulator instruction rate (inst/s) -host_tick_rate 60757564 # Simulator tick rate (ticks/s) -host_mem_usage 253712 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 16610 # Simulator instruction rate (inst/s) +host_tick_rate 28382842 # Simulator tick rate (ticks/s) +host_mem_usage 221852 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -54,90 +54,90 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.numCycles 19615 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2511 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1859 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2510 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1858 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 1876 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 752 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6264 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12675 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2511 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6260 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12668 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2510 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1020 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2829 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1652 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 2827 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1646 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1029 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2035 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11271 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.423476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.772468 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.423992 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.773203 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8442 74.90% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8435 74.90% 74.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 274 2.43% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 191 1.69% 79.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 247 2.19% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 241 2.14% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 319 2.83% 86.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 123 1.09% 87.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 122 1.08% 88.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1312 11.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 191 1.70% 79.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 246 2.18% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 240 2.13% 83.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 319 2.83% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 123 1.09% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 122 1.08% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1312 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11271 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.128014 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.646189 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6547 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 11262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127963 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.645832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6543 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1078 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2630 # Number of cycles decode is running +system.cpu.decode.RunCycles 2628 # Number of cycles decode is running system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 955 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 952 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14078 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 14071 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 955 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6833 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 952 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6829 # Number of cycles rename is idle system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2402 # Number of cycles rename is running +system.cpu.rename.RunCycles 2400 # Number of cycles rename is running system.cpu.rename.UnblockCycles 182 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13232 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 13225 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12797 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 60391 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 59071 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12790 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 60358 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 59038 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7108 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 7101 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 440 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2692 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2690 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1760 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11414 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9287 # Number of instructions issued +system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5147 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13929 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 5140 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13918 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11271 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.823973 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.824188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485862 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7571 67.17% 67.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1335 11.84% 79.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 851 7.55% 86.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 557 4.94% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 476 4.22% 95.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7565 67.17% 67.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1334 11.85% 79.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 849 7.54% 86.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 557 4.95% 91.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 476 4.23% 95.73% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 278 2.47% 98.20% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 148 1.31% 99.51% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 43 0.38% 99.89% # Number of insts issued each cycle @@ -145,7 +145,7 @@ system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11271 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11262 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.75% 2.75% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.75% # attempts to use FU when none available @@ -181,7 +181,7 @@ system.cpu.iq.fu_full::MemWrite 71 32.57% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5675 61.11% 61.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5672 61.11% 61.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7 0.08% 61.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.18% # Type of FU issued @@ -206,80 +206,80 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.18% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2324 25.02% 86.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1278 13.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2322 25.02% 86.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1278 13.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9287 # Type of FU issued -system.cpu.iq.rate 0.473464 # Inst issue rate +system.cpu.iq.FU_type_0::total 9282 # Type of FU issued +system.cpu.iq.rate 0.473209 # Inst issue rate system.cpu.iq.fu_busy_cnt 218 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023474 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30092 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16563 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8319 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.023486 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30073 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16544 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8314 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9465 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1491 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 955 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 952 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11449 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 11442 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 210 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2692 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2690 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1760 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 301 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 397 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8853 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2124 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 8848 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2122 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 434 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_refs 3346 # number of memory reference insts executed -system.cpu.iew.exec_branches 1462 # Number of branches executed +system.cpu.iew.exec_refs 3344 # number of memory reference insts executed +system.cpu.iew.exec_branches 1461 # Number of branches executed system.cpu.iew.exec_stores 1222 # Number of stores executed -system.cpu.iew.exec_rate 0.451338 # Inst execution rate -system.cpu.iew.wb_sent 8511 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8335 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3964 # num instructions producing a value -system.cpu.iew.wb_consumers 7808 # num instructions consuming a value +system.cpu.iew.exec_rate 0.451083 # Inst execution rate +system.cpu.iew.wb_sent 8506 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8330 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3963 # num instructions producing a value +system.cpu.iew.wb_consumers 7807 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.424930 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.507684 # average fanout of values written-back +system.cpu.iew.wb_rate 0.424675 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.507621 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5552 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5548 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.556266 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.365268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.556590 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.365529 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7976 77.31% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1088 10.55% 87.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 426 4.13% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 280 2.71% 94.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7969 77.29% 77.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1090 10.57% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 425 4.12% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 280 2.72% 94.69% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 183 1.77% 96.47% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 171 1.66% 98.13% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 67 0.65% 98.78% # Number of insts commited each cycle @@ -288,7 +288,7 @@ system.cpu.commit.committed_per_cycle::8 88 0.85% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10311 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed @@ -300,47 +300,47 @@ system.cpu.commit.int_insts 4985 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 88 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21363 # The number of ROB reads -system.cpu.rob.rob_writes 23555 # The number of ROB writes +system.cpu.rob.rob_reads 21353 # The number of ROB reads +system.cpu.rob.rob_writes 23544 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8344 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated system.cpu.cpi 3.417843 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.417843 # CPI: Total CPI of All Threads system.cpu.ipc 0.292582 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.292582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40304 # number of integer regfile reads -system.cpu.int_regfile_writes 8184 # number of integer regfile writes +system.cpu.int_regfile_reads 40279 # number of integer regfile reads +system.cpu.int_regfile_writes 8179 # number of integer regfile writes system.cpu.fp_regfile_reads 29 # number of floating regfile reads -system.cpu.misc_regfile_reads 15709 # number of misc regfile reads +system.cpu.misc_regfile_reads 15700 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.tagsinuse 150.950866 # Cycle average of tags in use -system.cpu.icache.total_refs 1669 # Total number of references to valid blocks. +system.cpu.icache.total_refs 1667 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.638514 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.631757 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::0 150.950866 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.073706 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1669 # number of ReadReq hits -system.cpu.icache.demand_hits 1669 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1669 # number of overall hits -system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses -system.cpu.icache.demand_misses 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12661500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12661500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12661500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2035 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.179853 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.179853 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.179853 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34594.262295 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34594.262295 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34594.262295 # average overall miss latency +system.cpu.icache.ReadReq_hits 1667 # number of ReadReq hits +system.cpu.icache.demand_hits 1667 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1667 # number of overall hits +system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses +system.cpu.icache.demand_misses 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 12617500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12617500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2031 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.179222 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.179222 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.179222 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34663.461538 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34663.461538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34663.461538 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,67 +350,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9939500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9939500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9939500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9940000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9940000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9940000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.145455 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.145455 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.145455 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33579.391892 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33579.391892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33579.391892 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33581.081081 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 92.326406 # Cycle average of tags in use -system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.512821 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 15.500000 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 92.326406 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.022541 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1791 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1789 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2400 # number of overall hits +system.cpu.dcache.demand_hits 2398 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2398 # number of overall hits system.cpu.dcache.ReadReq_misses 177 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses system.cpu.dcache.overall_misses 481 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5493000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5493500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 16198500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16198500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1968 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 16199000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16199000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1966 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2881 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2881 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.089939 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2879 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.090031 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.166956 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.166956 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31033.898305 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.167072 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.167072 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31036.723164 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33676.715177 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33676.715177 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33677.754678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33677.754678 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -430,30 +430,30 @@ system.cpu.dcache.WriteReq_mshr_misses 42 # nu system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4741000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4741000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.057927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057986 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.054148 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.054148 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28385.964912 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.054185 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.054185 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30391.025641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30391.025641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 191.048860 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 191.048911 # Cycle average of tags in use system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 191.048860 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 191.048911 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.005830 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits @@ -462,10 +462,10 @@ system.cpu.l2cache.ReadReq_misses 367 # nu system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12610500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12611500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14061000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14061000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 14062000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14062000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses @@ -474,10 +474,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.895122 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34361.035422 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34363.760218 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34378.973105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34378.973105 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34381.418093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34381.418093 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,19 +495,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 42 # nu system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11305500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11306000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 12622500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 12622500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31230.662983 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31232.044199 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index ad4f6b32e..44cfcef80 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index ba028db41..1aed5d989 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:04:50 -gem5 started Jul 8 2011 15:22:23 +gem5 compiled Sep 13 2011 11:17:24 +gem5 started Sep 13 2011 11:17:29 gem5 executing on u200439-lin.austin.arm.com command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index bde2424c6..dc1cbf29f 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000020 # Number of seconds simulated sim_ticks 19785000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27579 # Simulator instruction rate (inst/s) -host_tick_rate 93627553 # Simulator tick rate (ticks/s) -host_mem_usage 243928 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 4508 # Simulator instruction rate (inst/s) +host_tick_rate 15307212 # Simulator tick rate (ticks/s) +host_mem_usage 249516 # Number of bytes of host memory used +host_seconds 1.29 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index 6a2ff3124..d39ff7633 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index a0a2e036e..70bb08b97 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2011 01:24:08 -gem5 started Sep 9 2011 01:24:15 -gem5 executing on chips +gem5 compiled Sep 13 2011 11:17:24 +gem5 started Sep 13 2011 11:17:29 +gem5 executing on u200439-lin.austin.arm.com command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12273500 because target called exit() +Exiting @ tick 12272500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index eb0ece35d..d3b5afd1a 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12273500 # Number of ticks simulated +sim_ticks 12272500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39169 # Simulator instruction rate (inst/s) -host_tick_rate 92983194 # Simulator tick rate (ticks/s) -host_mem_usage 242872 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 4036 # Simulator instruction rate (inst/s) +host_tick_rate 9581124 # Simulator tick rate (ticks/s) +host_mem_usage 250068 # Number of bytes of host memory used +host_seconds 1.28 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,101 +27,101 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24548 # number of cpu cycles simulated +system.cpu.numCycles 24546 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1977 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1345 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 1975 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1580 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7914 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12271 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1977 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12258 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1975 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1189 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1783 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.972114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1781 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9597 76.03% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1250 9.90% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 93 0.74% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 870 6.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080536 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.499878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8103 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2859 # Number of cycles decode is running +system.cpu.decode.RunCycles 2857 # Number of cycles decode is running system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 739 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11438 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 739 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8274 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2742 # Number of cycles rename is running +system.cpu.rename.RunCycles 2740 # Number of cycles rename is running system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13124 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13110 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 18 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2349 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8651 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7822 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7815 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1815 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.619663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9267 73.41% 73.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1321 10.47% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 831 6.58% 90.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 511 4.05% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.83% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 203 1.61% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 83 0.66% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available @@ -157,104 +157,104 @@ system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4598 58.78% 58.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2131 27.24% 86.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1085 13.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7822 # Type of FU issued -system.cpu.iq.rate 0.318641 # Inst issue rate +system.cpu.iq.FU_type_0::total 7815 # Type of FU issued +system.cpu.iq.rate 0.318382 # Inst issue rate system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018665 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28459 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11666 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7121 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7966 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1185 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 739 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10044 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2349 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7537 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2031 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1380 # number of nop insts executed -system.cpu.iew.exec_refs 3091 # number of memory reference insts executed +system.cpu.iew.exec_nop 1378 # number of nop insts executed +system.cpu.iew.exec_refs 3087 # number of memory reference insts executed system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1060 # Number of stores executed -system.cpu.iew.exec_rate 0.307031 # Inst execution rate -system.cpu.iew.wb_sent 7215 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7123 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2761 # num instructions producing a value -system.cpu.iew.wb_consumers 3949 # num instructions consuming a value +system.cpu.iew.exec_stores 1059 # Number of stores executed +system.cpu.iew.exec_rate 0.306812 # Inst execution rate +system.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7118 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2758 # num instructions producing a value +system.cpu.iew.wb_consumers 3946 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.290166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699164 # average fanout of values written-back +system.cpu.iew.wb_rate 0.289986 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4210 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11884 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490239 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.276602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9485 79.81% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 8.13% 87.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.52% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle @@ -264,7 +264,7 @@ system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle system.cpu.commit.count 5826 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed @@ -276,47 +276,47 @@ system.cpu.commit.int_insts 5124 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21805 # The number of ROB reads -system.cpu.rob.rob_writes 20822 # The number of ROB writes +system.cpu.rob.rob_reads 21779 # The number of ROB reads +system.cpu.rob.rob_writes 20794 # The number of ROB writes system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11925 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.749081 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.749081 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210567 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210567 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10287 # number of integer regfile reads -system.cpu.int_regfile_writes 4991 # number of integer regfile writes +system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads +system.cpu.ipc 0.210584 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10280 # number of integer regfile reads +system.cpu.int_regfile_writes 4987 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 153 # number of misc regfile reads +system.cpu.misc_regfile_reads 154 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use -system.cpu.icache.total_refs 1364 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use +system.cpu.icache.total_refs 1363 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.059524 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 161.223747 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 161.224498 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1364 # number of ReadReq hits -system.cpu.icache.demand_hits 1364 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1364 # number of overall hits -system.cpu.icache.ReadReq_misses 419 # number of ReadReq misses -system.cpu.icache.demand_misses 419 # number of demand (read+write) misses -system.cpu.icache.overall_misses 419 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15179500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15179500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15179500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1783 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1783 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1783 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.234997 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.234997 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.234997 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36227.923628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36227.923628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36227.923628 # average overall miss latency +system.cpu.icache.ReadReq_hits 1363 # number of ReadReq hits +system.cpu.icache.demand_hits 1363 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1363 # number of overall hits +system.cpu.icache.ReadReq_misses 418 # number of ReadReq misses +system.cpu.icache.demand_misses 418 # number of demand (read+write) misses +system.cpu.icache.overall_misses 418 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15148000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15148000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15148000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1781 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1781 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1781 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.234700 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.234700 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.234700 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36239.234450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36239.234450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36239.234450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,9 +326,9 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 82 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 82 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 82 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses @@ -337,9 +337,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.188446 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.188446 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.188446 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.188658 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.188658 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.188658 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency @@ -348,37 +348,37 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.122056 # Cycle average of tags in use -system.cpu.dcache.total_refs 2382 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use +system.cpu.dcache.total_refs 2380 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.774648 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.122056 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 92.121984 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1804 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1802 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits -system.cpu.dcache.demand_hits 2382 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2382 # number of overall hits -system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses +system.cpu.dcache.demand_hits 2380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2380 # number of overall hits +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses -system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 481 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4801000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11505500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16306500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16306500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1938 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4767500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11508000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 16275500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16275500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1935 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.069143 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.068734 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.168006 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.168006 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35828.358209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33157.060519 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33901.247401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33901.247401 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.167832 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.167832 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33907.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33907.291667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,39 +388,39 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 42 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 339 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 338 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 338 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5107500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5107500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1836000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5108000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5108000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.046956 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.047028 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.049598 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.049598 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.049650 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.049650 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35990.196078 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.520650 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.520650 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 221.521956 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits @@ -429,8 +429,8 @@ system.cpu.l2cache.ReadReq_misses 424 # nu system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14561500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1760000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1760500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency 16321500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 16321500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) @@ -441,8 +441,8 @@ system.cpu.l2cache.ReadReq_miss_rate 0.992974 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34343.160377 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34509.803922 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34519.607843 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency 34361.052632 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 34361.052632 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index fda15903b..4d964406e 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -67,7 +67,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index 1b8822a01..9509c6985 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2011 01:24:08 -gem5 started Sep 9 2011 01:24:15 -gem5 executing on chips +gem5 compiled Sep 13 2011 11:17:24 +gem5 started Sep 13 2011 11:17:29 +gem5 executing on u200439-lin.austin.arm.com command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index 8495d4b7b..462a34e56 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000003 # Number of seconds simulated sim_ticks 2913500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 550881 # Simulator instruction rate (inst/s) -host_tick_rate 274282730 # Simulator tick rate (ticks/s) -host_mem_usage 232848 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 4455 # Simulator instruction rate (inst/s) +host_tick_rate 2227266 # Simulator tick rate (ticks/s) +host_mem_usage 240420 # Number of bytes of host memory used +host_seconds 1.31 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -37,7 +37,7 @@ system.cpu.num_func_calls 194 # nu system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls system.cpu.num_int_insts 5126 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7300 # number of times the integer registers were read +system.cpu.num_int_register_reads 7301 # number of times the integer registers were read system.cpu.num_int_register_writes 3409 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 41938cc87..8c0fe7266 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -64,7 +64,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout index 12fac784c..fc1b9eeff 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2011 01:24:08 -gem5 started Sep 9 2011 01:24:15 -gem5 executing on chips +gem5 compiled Sep 13 2011 11:17:24 +gem5 started Sep 13 2011 11:17:29 +gem5 executing on u200439-lin.austin.arm.com command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 0e750eb72..1ded2ae9a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000293 # Number of seconds simulated sim_ticks 292960 # Number of ticks simulated sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 24172 # Simulator instruction rate (inst/s) -host_tick_rate 1215173 # Simulator tick rate (ticks/s) -host_mem_usage 251116 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 9604 # Simulator instruction rate (inst/s) +host_tick_rate 482836 # Simulator tick rate (ticks/s) +host_mem_usage 258552 # Number of bytes of host memory used +host_seconds 0.61 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -37,7 +37,7 @@ system.cpu.num_func_calls 194 # nu system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls system.cpu.num_int_insts 5126 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7300 # number of times the integer registers were read +system.cpu.num_int_register_reads 7301 # number of times the integer registers were read system.cpu.num_int_register_writes 3409 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 383b176d8..4ab4dac25 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -170,7 +170,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 6cd1e0d5c..80781ba32 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2011 01:24:08 -gem5 started Sep 9 2011 01:24:15 -gem5 executing on chips +gem5 compiled Sep 13 2011 11:17:24 +gem5 started Sep 13 2011 11:17:29 +gem5 executing on u200439-lin.austin.arm.com command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index d92612e60..8e7fe8774 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000032 # Number of seconds simulated sim_ticks 32088000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 266984 # Simulator instruction rate (inst/s) -host_tick_rate 1467506046 # Simulator tick rate (ticks/s) -host_mem_usage 241568 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 4536 # Simulator instruction rate (inst/s) +host_tick_rate 24978496 # Simulator tick rate (ticks/s) +host_mem_usage 249136 # Number of bytes of host memory used +host_seconds 1.29 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -37,7 +37,7 @@ system.cpu.num_func_calls 194 # nu system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls system.cpu.num_int_insts 5126 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7300 # number of times the integer registers were read +system.cpu.num_int_register_reads 7301 # number of times the integer registers were read system.cpu.num_int_register_writes 3409 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index 7ab760d62..43fbd9cf3 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 66b7170d9..1cc0d7d05 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:01:24 -gem5 started Jul 16 2011 00:22:08 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index f6f7897f3..1b6fe9e6f 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000011 # Number of seconds simulated sim_ticks 11087000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48237 # Simulator instruction rate (inst/s) -host_tick_rate 54512378 # Simulator tick rate (ticks/s) -host_mem_usage 248340 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 51481 # Simulator instruction rate (inst/s) +host_tick_rate 58182623 # Simulator tick rate (ticks/s) +host_mem_usage 209228 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 22175 # number of cpu cycles simulated @@ -20,17 +20,17 @@ system.cpu.BPredUnit.BTBHits 995 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 5894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 5895 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 14000 # Number of instructions fetch has processed system.cpu.fetch.Branches 3057 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2223 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 2221 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1500 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 1891 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 13088 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.930776 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.218766 # Number of instructions fetched each cycle (Total) @@ -52,48 +52,48 @@ system.cpu.fetch.branchRate 0.137858 # Nu system.cpu.fetch.rate 0.631342 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3564 # Number of cycles decode is running +system.cpu.decode.RunCycles 3565 # Number of cycles decode is running system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1713 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24084 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1713 # Number of cycles rename is squashing +system.cpu.decode.SquashCycles 1712 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24090 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1712 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 6535 # Number of cycles rename is idle system.cpu.rename.BlockCycles 523 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 524 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3364 # Number of cycles rename is running +system.cpu.rename.RunCycles 3365 # Number of cycles rename is running system.cpu.rename.UnblockCycles 429 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 22712 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 271 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21249 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47660 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47644 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 272 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21252 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 47663 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 47647 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11881 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 11884 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1609 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 1613 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2239 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1783 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 20542 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16959 # Number of instructions issued +system.cpu.iq.iqInstsIssued 16960 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13000 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 12997 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.295767 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.295844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.003369 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1107 8.46% 69.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1007 7.69% 77.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1006 7.69% 77.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 734 5.61% 82.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle @@ -138,7 +138,7 @@ system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13642 80.44% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued @@ -171,30 +171,30 @@ system.cpu.iq.FU_type_0::MemRead 1844 10.87% 91.33% # Ty system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16959 # Type of FU issued -system.cpu.iq.rate 0.764780 # Inst issue rate +system.cpu.iq.FU_type_0::total 16960 # Type of FU issued +system.cpu.iq.rate 0.764825 # Inst issue rate system.cpu.iq.fu_busy_cnt 141 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008314 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 47202 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30805 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15753 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 47204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30804 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15755 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17092 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17093 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1183 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1713 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1712 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ @@ -204,37 +204,37 @@ system.cpu.iew.iewDispStoreInsts 1783 # Nu system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 523 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16098 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 16100 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 861 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3105 # number of memory reference insts executed system.cpu.iew.exec_branches 1601 # Number of branches executed system.cpu.iew.exec_stores 1363 # Number of stores executed -system.cpu.iew.exec_rate 0.725953 # Inst execution rate -system.cpu.iew.wb_sent 15916 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15757 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10536 # num instructions producing a value -system.cpu.iew.wb_consumers 15696 # num instructions consuming a value +system.cpu.iew.exec_rate 0.726043 # Inst execution rate +system.cpu.iew.wb_sent 15918 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15759 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10538 # num instructions producing a value +system.cpu.iew.wb_consumers 15699 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.710575 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.671254 # average fanout of values written-back +system.cpu.iew.wb_rate 0.710665 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.671253 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.commit.commitSquashedInsts 10766 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 497 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.862330 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.686905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.862254 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.686850 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7943 69.83% 69.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1088 9.56% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7944 69.83% 69.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1088 9.56% 79.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 574 5.05% 84.44% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 883 7.76% 92.20% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 343 3.02% 95.22% # Number of insts commited each cycle @@ -245,7 +245,7 @@ system.cpu.commit.committed_per_cycle::8 187 1.64% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11376 # Number of insts commited each cycle system.cpu.commit.count 9809 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed @@ -257,8 +257,8 @@ system.cpu.commit.int_insts 9714 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 187 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 31763 # The number of ROB reads -system.cpu.rob.rob_writes 42898 # The number of ROB writes +system.cpu.rob.rob_reads 31764 # The number of ROB reads +system.cpu.rob.rob_writes 42896 # The number of ROB writes system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 9087 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 9809 # Number of Instructions Simulated @@ -268,9 +268,9 @@ system.cpu.cpi_total 2.260679 # CP system.cpu.ipc 0.442345 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.442345 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 23665 # number of integer regfile reads -system.cpu.int_regfile_writes 14643 # number of integer regfile writes +system.cpu.int_regfile_writes 14645 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7210 # number of misc regfile reads +system.cpu.misc_regfile_reads 7211 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.tagsinuse 145.144237 # Cycle average of tags in use system.cpu.icache.total_refs 1527 # Total number of references to valid blocks. |