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authorAli Saidi <saidi@eecs.umich.edu>2011-09-13 12:58:08 -0400
committerAli Saidi <saidi@eecs.umich.edu>2011-09-13 12:58:08 -0400
commit649c239ceef2d107fae253b1008c6f214f242d73 (patch)
tree06edeb7bfa7b9d1e9167b9cb80f7f9600d41b9a0 /tests/quick/00.hello/ref
parentbb921b1459ef3ec55f9cea4ac8d203cd3c801cfd (diff)
downloadgem5-649c239ceef2d107fae253b1008c6f214f242d73.tar.xz
LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed between two subsequent loads, instead of just when loads go out-of-order to the same address. While not very common in the case of Alpha, with an architecture with a hardware table walker this can happen reasonably frequently beacuse a translation will miss and start a table walk and before the CPU re-schedules the faulting instruction another one will pass it to the same address (or cache block depending on the dendency checking). This patch has been tested with a couple of self-checking hand crafted programs to stress ordering between two cores. The performance improvement on SPEC benchmarks can be substantial (2-10%).
Diffstat (limited to 'tests/quick/00.hello/ref')
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