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authorSteve Reinhardt <stever@eecs.umich.edu>2006-09-05 16:24:47 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-09-05 16:24:47 -0400
commit6c7a490c2b779ea45adfc5708f50aa16718582e4 (patch)
tree3633153645f9f885e8155ba740ef7aaa1a221650 /tests/quick/00.hello/ref
parent89f0bc9e4c6e1c0bc58f5f5a88cdac5889758b1f (diff)
downloadgem5-6c7a490c2b779ea45adfc5708f50aa16718582e4.tar.xz
Update reference config.ini files to include port mappings.
--HG-- extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263
Diffstat (limited to 'tests/quick/00.hello/ref')
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini11
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt12
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini4
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini11
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt12
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini11
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini4
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout6
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini11
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini11
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt10
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stdout4
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini4
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout4
27 files changed, 131 insertions, 60 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 2b85e53f6..c3a59fbce 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -121,6 +121,8 @@ trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -159,6 +161,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.fuPool]
type=FUPool
@@ -334,6 +338,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -372,10 +378,13 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -389,12 +398,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index 3814e38d1..5d4f9235a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 420 # Nu
global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
global.BPredUnit.lookups 2256 # Number of BP lookups
global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 34296 # Simulator instruction rate (inst/s)
-host_mem_usage 160076 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
-host_tick_rate 41824 # Simulator tick rate (ticks/s)
+host_inst_rate 41797 # Simulator instruction rate (inst/s)
+host_mem_usage 160344 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 50948 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
@@ -170,8 +170,8 @@ system.cpu.icache.ReadReq_mshr_hits 6 # nu
system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 907b15392..fbb329a2f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 1 2006 16:10:44
-M5 started Fri Sep 1 16:23:41 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:12 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Exiting @ tick 6870 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index a530874f5..f84372165 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
index 72cf4f4f2..e3cd05fb0 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 108728 # Simulator instruction rate (inst/s)
-host_mem_usage 147156 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 107873 # Simulator tick rate (ticks/s)
+host_inst_rate 74000 # Simulator instruction rate (inst/s)
+host_mem_usage 148088 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 73591 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
index 88509858c..17eea9aed 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 24 2006 13:09:55
-M5 started Thu Aug 24 14:29:33 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:14 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Exiting @ tick 5641 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index fe8183125..80d2a27e1 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -66,6 +66,8 @@ max_loads_any_thread=0
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -104,6 +106,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
@@ -142,6 +146,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -180,10 +186,13 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -197,12 +206,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 2397e59b5..fe2cd43a5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 73848 # Simulator instruction rate (inst/s)
-host_mem_usage 159612 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 107959 # Simulator tick rate (ticks/s)
+host_inst_rate 113478 # Simulator instruction rate (inst/s)
+host_mem_usage 159608 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 165749 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
@@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu
system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1632 # number of overall hits
system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses
@@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index be2f32831..7104aa0ce 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:14 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:15 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Exiting @ tick 8312 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 388ddf7b6..790ae6ab3 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -121,6 +121,8 @@ trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -159,6 +161,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.fuPool]
type=FUPool
@@ -334,6 +338,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -372,10 +378,13 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -389,12 +398,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index 5c59263ac..db582e731 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu
global.BPredUnit.condPredicted 441 # Number of conditional branches predicted
global.BPredUnit.lookups 888 # Number of BP lookups
global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
-host_inst_rate 22611 # Simulator instruction rate (inst/s)
-host_mem_usage 159596 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-host_tick_rate 27259 # Simulator tick rate (ticks/s)
+host_inst_rate 26468 # Simulator instruction rate (inst/s)
+host_mem_usage 159864 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 31894 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index 04a06d3ab..708b9587a 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 1 2006 16:10:44
-M5 started Fri Sep 1 16:23:45 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:16 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Exiting @ tick 2886 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index d845c0efb..1ec052afb 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
index 2317e88dc..b4747f1f4 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 58510 # Simulator instruction rate (inst/s)
-host_mem_usage 146720 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 57971 # Simulator tick rate (ticks/s)
+host_inst_rate 46556 # Simulator instruction rate (inst/s)
+host_mem_usage 147672 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 46204 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
index d7cbe766c..438e330f5 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 18 2006 00:06:43
-M5 started Fri Aug 18 00:12:48 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:18 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Exiting @ tick 2577 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 5f05f07dd..e833d841e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -66,6 +66,8 @@ max_loads_any_thread=0
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -104,6 +106,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
@@ -142,6 +146,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -180,10 +186,13 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -197,12 +206,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index ee76bf8d8..47bcc1b3c 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5953 # Simulator instruction rate (inst/s)
-host_mem_usage 159132 # Number of bytes of host memory used
-host_seconds 0.43 # Real time elapsed on the host
-host_tick_rate 8713 # Simulator tick rate (ticks/s)
+host_inst_rate 73626 # Simulator instruction rate (inst/s)
+host_mem_usage 159128 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 106590 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index f4d7a3959..4a02e57f0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:22 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:18 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Exiting @ tick 3777 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index f0eb69e7f..2c82b8c1a 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
index a45e5a877..b70a6ee17 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 124620 # Simulator instruction rate (inst/s)
-host_mem_usage 147356 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 122794 # Simulator tick rate (ticks/s)
+host_inst_rate 90956 # Simulator instruction rate (inst/s)
+host_mem_usage 147380 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 90353 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index 12a95eebc..f5b9c8fd7 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 18 2006 00:09:15
-M5 started Fri Aug 18 00:12:56 2006
+M5 compiled Sep 5 2006 15:37:09
+M5 started Tue Sep 5 15:46:32 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
Exiting @ tick 5656 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index ab77b14a7..040735f2c 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -66,6 +66,8 @@ max_loads_any_thread=0
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -104,6 +106,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
@@ -142,6 +146,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -180,10 +186,13 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -197,12 +206,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index 54771832b..5d054b950 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 289509 # Simulator instruction rate (inst/s)
+host_inst_rate 129834 # Simulator instruction rate (inst/s)
host_mem_usage 158964 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 429531 # Simulator tick rate (ticks/s)
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 194881 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
@@ -90,8 +90,8 @@ system.cpu.icache.ReadReq_misses 303 # nu
system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index fd27ee686..11009935d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 21 2006 14:43:46
-M5 started Mon Aug 21 14:44:00 2006
+M5 compiled Sep 5 2006 15:37:09
+M5 started Tue Sep 5 15:46:32 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Exiting @ tick 8573 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index c22373526..082415a7f 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@ system=system
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
index 52a75def4..9bfb2fec9 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 79435 # Simulator instruction rate (inst/s)
-host_mem_usage 147292 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 78854 # Simulator tick rate (ticks/s)
+host_inst_rate 61348 # Simulator instruction rate (inst/s)
+host_mem_usage 147288 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 60991 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4483 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
index 0730d4b3e..38eb82c8b 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 24 2006 13:31:50
-M5 started Thu Aug 24 14:29:35 2006
+M5 compiled Sep 5 2006 15:39:50
+M5 started Tue Sep 5 15:49:24 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Exiting @ tick 4482 because target called exit()