diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/quick/00.hello/ref | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/quick/00.hello/ref')
17 files changed, 1095 insertions, 1096 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 94e787873..3181a01cf 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:42:32 -M5 revision 1633bdfc3b0a 7062 default qtip regression_update tip -M5 started Apr 10 2010 23:42:34 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:43:43 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31225500 because target called exit() +Exiting @ tick 31242000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index adbfbe35c..8b050d9d7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30166 # Simulator instruction rate (inst/s) -host_mem_usage 153332 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 146878557 # Simulator tick rate (ticks/s) +host_inst_rate 29156 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 142052352 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31225500 # Number of ticks simulated +sim_ticks 31242000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 202 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 582 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHits 94 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 314 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 125 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 957 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 895 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 751 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 721 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 345 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.predictedNotTaken 829 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 237 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Decode-Unit.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 4340 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 4354 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 447 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 165 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.069493 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 13895 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 524 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 134 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.069457 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 13850 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 6404 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 2 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 1 # Number of Multiply Requests Processed. system.cpu.RegFile-Manager.instReqsProcessed 19960 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 22.223468 # Percentage of cycles cpu is active +system.cpu.activity 22.272545 # Percentage of cycles cpu is active system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.752030 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.752030 # CPI: Total CPI of All Threads +system.cpu.cpi 9.757183 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.757183 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56342.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53342.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56336.842105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53336.842105 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5352500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5352000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5067500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56063.218391 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53063.218391 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56057.471264 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53057.471264 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4877500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4877000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4616000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10230000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10229000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9684000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9683000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025299 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.624059 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025306 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.651945 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10230000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10229000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9684000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9683000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.624059 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.651945 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -119,73 +119,73 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 7358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55544.850498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52868.421053 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7057 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16719000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.040908 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 7296 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55536.544850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6995 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16716500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.041255 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 301 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15067500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.038733 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15066000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.039062 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 24.848592 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24.630282 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7358 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency -system.cpu.icache.demand_hits 7057 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16719000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.040908 # miss rate for demand accesses +system.cpu.icache.demand_accesses 7296 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency +system.cpu.icache.demand_hits 6995 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16716500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.041255 # miss rate for demand accesses system.cpu.icache.demand_misses 301 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15067500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.038733 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15066000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.039062 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063597 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.247335 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7358 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.063623 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 130.299954 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7296 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7057 # number of overall hits -system.cpu.icache.overall_miss_latency 16719000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.040908 # miss rate for overall accesses +system.cpu.icache.overall_hits 6995 # number of overall hits +system.cpu.icache.overall_miss_latency 16716500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.041255 # miss rate for overall accesses system.cpu.icache.overall_misses 301 # number of overall misses system.cpu.icache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15067500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.038733 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15066000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.039062 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.247335 # Cycle average of tags in use -system.cpu.icache.total_refs 7057 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 130.299954 # Cycle average of tags in use +system.cpu.icache.total_refs 6995 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 7356 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 48573 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102543 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102543 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 7294 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 48568 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.102489 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.102489 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 7375 # ITB accesses +system.cpu.itb.fetch_accesses 7313 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 7358 # ITB hits +system.cpu.itb.fetch_hits 7296 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,19 +196,19 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52061.643836 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52054.794521 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3800500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3800000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52069.920844 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52065.963061 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15139000 # number of ReadReq MSHR miss cycles @@ -232,10 +232,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23535000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23533000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -245,14 +245,14 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.381905 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005537 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 181.445272 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23535000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23533000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses system.cpu.l2cache.overall_misses 452 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -264,32 +264,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.381905 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.445272 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62452 # number of cpu cycles simulated -system.cpu.runCycles 13879 # Number of cycles cpu stages are processed. +system.cpu.numCycles 62485 # number of cpu cycles simulated +system.cpu.runCycles 13917 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55077 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 7375 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.809069 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55915 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6537 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.467239 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 55982 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 55172 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 7313 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 11.703609 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 55931 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6554 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.488917 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 56015 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.359956 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60399 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.354485 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 60432 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.287325 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 56048 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.285589 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 56081 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.254275 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62452 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.248860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 62485 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1b5a762f3..409d22ab8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 0bdde157a..2c74abf7c 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:54 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 01:04:08 -M5 executing on SC2B0619 -command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:59:38 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12474500 because target called exit() +Exiting @ tick 12497500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7fffd3b0b..1208848c5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,259 +1,259 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 104903 # Simulator instruction rate (inst/s) -host_mem_usage 190976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 203948336 # Simulator tick rate (ticks/s) +host_inst_rate 84020 # Simulator instruction rate (inst/s) +host_mem_usage 204400 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 163850067 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12474500 # Number of ticks simulated +sim_ticks 12497500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2263 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2245 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12417 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515664 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.304890 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 9514 76.62% 76.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% 89.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% 93.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% 95.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% 97.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9528 76.65% 76.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1629 13.10% 89.75% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 491 3.95% 93.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 259 2.08% 95.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 156 1.25% 97.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.88% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% 99.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 49 0.39% 99.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12417 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses +system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses -system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses +system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2104 # number of overall hits -system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses -system.cpu.dcache.overall_misses 554 # number of overall misses -system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2103 # number of overall hits +system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses +system.cpu.dcache.overall_misses 544 # number of overall misses +system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use -system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use +system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2951 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2948 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2890 # DTB hits +system.cpu.dtb.data_hits 2887 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1876 # DTB read accesses +system.cpu.dtb.read_accesses 1865 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1840 # DTB read hits +system.cpu.dtb.read_hits 1829 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.write_accesses 1083 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1050 # DTB write hits +system.cpu.dtb.write_hits 1058 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched -system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 501 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched +system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 10844 81.45% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 252 1.89% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 238 1.79% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 230 1.73% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 272 2.04% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 162 1.22% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 232 1.74% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 129 0.97% 92.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 955 7.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 245 1.84% 83.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 221 1.66% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 185 1.39% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 233 1.75% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 164 1.23% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 228 1.71% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 133 1.00% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency -system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses -system.cpu.icache.demand_misses 424 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses +system.cpu.icache.demand_misses 426 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1378 # number of overall hits -system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses -system.cpu.icache.overall_misses 424 # number of overall misses -system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1366 # number of overall hits +system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses +system.cpu.icache.overall_misses 426 # number of overall misses +system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use -system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use +system.cpu.icache.total_refs 1366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1450 # Number of branches executed -system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate -system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1077 # Number of stores executed +system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1448 # Number of branches executed +system.cpu.iew.EXEC:nop 83 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate +system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1085 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6020 # num instructions consuming a value -system.cpu.iew.WB:count 8734 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back +system.cpu.iew.WB:consumers 6049 # num instructions consuming a value +system.cpu.iew.WB:count 8759 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4491 # num instructions producing a value -system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle -system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4508 # num instructions producing a value +system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle +system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores @@ -262,77 +262,77 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6254 66.92% 66.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1986 21.25% 88.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1100 11.77% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9345 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 14 13.33% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 56 53.33% 66.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% 81.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% 89.38% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% 94.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% 97.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% 98.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9142 68.58% 68.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1697 12.73% 81.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1062 7.97% 89.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 730 5.48% 94.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 359 2.69% 97.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 188 1.41% 98.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 105 0.79% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 36 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate -system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate +system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1838 # ITB accesses +system.cpu.itb.fetch_accesses 1827 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1802 # ITB hits -system.cpu.itb.fetch_misses 36 # ITB misses +system.cpu.itb.fetch_hits 1792 # ITB hits +system.cpu.itb.fetch_misses 35 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -342,31 +342,31 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -378,31 +378,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -410,32 +410,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 24950 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24996 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index c164849b4..73089a2aa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 703e5cb77..95c4493ba 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:44:06 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:10:59 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7183000 because target called exit() +Exiting @ tick 7285000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 48416d4fa..c49e5f817 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,337 +1,337 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86395 # Simulator instruction rate (inst/s) -host_mem_usage 189960 # Number of bytes of host memory used +host_inst_rate 87095 # Simulator instruction rate (inst/s) +host_mem_usage 203396 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 257307637 # Simulator tick rate (ticks/s) +host_tick_rate 263805903 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7183000 # Number of ticks simulated +sim_ticks 7285000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 198 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 684 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 674 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 447 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 859 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 463 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 916 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 178 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6197 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.415685 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 6323 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.407402 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.198077 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% 84.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% 88.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% 94.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% 97.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% 98.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% 99.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% 99.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 38 0.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 5366 84.86% 84.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 262 4.14% 89.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 338 5.35% 94.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 131 2.07% 96.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 72 1.14% 97.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 64 1.01% 98.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.51% 99.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 19 0.30% 99.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 39 0.62% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6323 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1946 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.104315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.104315 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35822.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35663.934426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 505 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3224000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.151261 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2175500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.102521 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37219.626168 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37702.702703 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3982500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1395000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.600000 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.demand_accesses 889 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36581.218274 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses -system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7206500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.221597 # miss rate for demand accesses +system.cpu.dcache.demand_misses 197 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 99 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.110236 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011202 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 45.884316 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.occ_%::0 0.011290 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 46.245716 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 889 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36581.218274 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674 # number of overall hits -system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses -system.cpu.dcache.overall_misses 193 # number of overall misses -system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_hits 692 # number of overall hits +system.cpu.dcache.overall_miss_latency 7206500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.221597 # miss rate for overall accesses +system.cpu.dcache.overall_misses 197 # number of overall misses +system.cpu.dcache.overall_mshr_hits 99 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.110236 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use -system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.245716 # Cycle average of tags in use +system.cpu.dcache.total_refs 731 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 169 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 142 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 5018 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5179 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 974 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 367 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 971 # DTB accesses +system.cpu.dtb.data_accesses 1010 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 946 # DTB hits -system.cpu.dtb.data_misses 25 # DTB misses +system.cpu.dtb.data_hits 979 # DTB hits +system.cpu.dtb.data_misses 31 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 611 # DTB read accesses +system.cpu.dtb.read_accesses 638 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 600 # DTB read hits -system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 360 # DTB write accesses +system.cpu.dtb.read_hits 623 # DTB read hits +system.cpu.dtb.read_misses 15 # DTB read misses +system.cpu.dtb.write_accesses 372 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 346 # DTB write hits -system.cpu.dtb.write_misses 14 # DTB write misses -system.cpu.fetch.Branches 859 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 747 # Number of cache lines fetched -system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 239 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.826134 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.219931 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 356 # DTB write hits +system.cpu.dtb.write_misses 16 # DTB write misses +system.cpu.fetch.Branches 916 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 789 # Number of cache lines fetched +system.cpu.fetch.Cycles 1801 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 119 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5736 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 250 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.062865 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 789 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 368 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.393659 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.857399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271719 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 5595 85.71% 85.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 36 0.55% 86.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 100 1.53% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 69 1.06% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 130 1.99% 90.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 72 1.10% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 45 0.69% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 48 0.74% 93.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 433 6.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 5707 85.31% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 48 0.72% 86.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 101 1.51% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 74 1.11% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 57 0.85% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 51 0.76% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 51 0.76% 92.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 478 7.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6528 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 6690 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 789 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36081.196581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.154696 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 555 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8443000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.296578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6391500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.229404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.066298 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency -system.cpu.icache.demand_hits 512 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses -system.cpu.icache.demand_misses 235 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 789 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36081.196581 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency +system.cpu.icache.demand_hits 555 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8443000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.296578 # miss rate for demand accesses +system.cpu.icache.demand_misses 234 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6391500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.229404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.043324 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 88.727286 # Average occupied blocks per context -system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.043805 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 89.711886 # Average occupied blocks per context +system.cpu.icache.overall_accesses 789 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36081.196581 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 512 # number of overall hits -system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses -system.cpu.icache.overall_misses 235 # number of overall misses -system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 555 # number of overall hits +system.cpu.icache.overall_miss_latency 8443000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.296578 # miss rate for overall accesses +system.cpu.icache.overall_misses 234 # number of overall misses +system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6391500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.229404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use -system.cpu.icache.total_refs 512 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 89.711886 # Cycle average of tags in use +system.cpu.icache.total_refs 555 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 584 # Number of branches executed -system.cpu.iew.EXEC:nop 286 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate -system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 360 # Number of stores executed +system.cpu.idleCycles 7881 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 607 # Number of branches executed +system.cpu.iew.EXEC:nop 310 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.241370 # Inst execution rate +system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 372 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1896 # num instructions consuming a value -system.cpu.iew.WB:count 3311 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back +system.cpu.iew.WB:consumers 1984 # num instructions consuming a value +system.cpu.iew.WB:count 3409 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.798891 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1509 # num instructions producing a value -system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle -system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1585 # num instructions producing a value +system.cpu.iew.WB:rate 0.233958 # insts written-back per cycle +system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 787 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispStoreInsts 432 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4536 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 641 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 117 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3517 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 372 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 138 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 110 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads +system.cpu.ipc 0.163819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.163819 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2506 71.31% 71.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 639 18.18% 89.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 368 10.47% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2590 71.27% 71.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 666 18.33% 89.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 377 10.37% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3514 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 3634 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009631 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.94% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 11 32.35% 35.29% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 22 64.71% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 6690 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543199 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215587 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% 77.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% 86.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% 91.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% 95.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% 97.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% 99.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% 99.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5134 76.74% 76.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 621 9.28% 86.02% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 357 5.34% 91.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 240 3.59% 94.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 184 2.75% 97.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 102 1.52% 99.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 36 0.54% 99.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.16% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6528 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate -system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 6690 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.249399 # Inst issue rate +system.cpu.iq.iqInstsAdded 4220 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3634 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 874 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 776 # ITB accesses +system.cpu.itb.fetch_accesses 818 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 747 # ITB hits +system.cpu.itb.fetch_hits 789 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,21 +351,21 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34324.380165 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 8306500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31107.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 435500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -377,10 +377,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34349.624060 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9137000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -390,14 +390,14 @@ system.cpu.l2cache.demand_mshr_misses 266 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003380 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 110.762790 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003416 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 111.924793 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34349.624060 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9137000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -409,32 +409,31 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 111.924793 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 411 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 14367 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 787 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 432 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 14571 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IdleCycles 5259 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5438 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4848 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3462 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 895 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 367 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 16 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1694 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 80 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index aa3193437..12732e5e1 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 23 2010 00:25:27 -M5 revision ba1ff0a71710+ 7040+ default tip -M5 started Mar 23 2010 00:25:28 -M5 executing on zooks +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 6c70d7ee8..76dc624e3 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30626 # Simulator instruction rate (inst/s) -host_mem_usage 154136 # Number of bytes of host memory used +host_inst_rate 30301 # Simulator instruction rate (inst/s) +host_mem_usage 205096 # Number of bytes of host memory used host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 153245779 # Simulator tick rate (ticks/s) +host_tick_rate 151651964 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated sim_ticks 29206500 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.BTBHits 0 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 641 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBLookups 499 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.Branch-Predictor.condIncorrect 666 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index a93b6565a..a56ef0667 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -412,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index f2820f9aa..0c4704bfb 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:23 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 14060500 because target called exit() +Exiting @ tick 14021500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index e79cbdaa4..ab93396d9 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82851 # Simulator instruction rate (inst/s) -host_mem_usage 191760 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 224354167 # Simulator tick rate (ticks/s) +host_inst_rate 60574 # Simulator instruction rate (inst/s) +host_mem_usage 205208 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 163793003 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14060500 # Number of ticks simulated +sim_ticks 14021500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 572 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1960 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1900 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 751 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1593 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2416 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 404 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1589 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2405 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 65 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14561 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.400110 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.121131 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14488 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.402126 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.127822 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 11999 82.41% 82.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1213 8.33% 90.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 529 3.63% 94.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 291 2.00% 96.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 294 2.02% 98.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 71 0.49% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 37 0.25% 99.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 65 0.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11934 82.37% 82.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1210 8.35% 90.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 523 3.61% 94.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 292 2.02% 96.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 294 2.03% 98.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 67 0.46% 98.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 37 0.26% 99.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 69 0.48% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14561 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14488 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed system.cpu.commit.COM:loads 1164 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2089 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 620 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 6017 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5972 # The number of squashed insts skipped by commit system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 5.440511 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.440511 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2321 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34074.626866 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36043.956044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2187 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4566000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.057734 # miss rate for ReadReq accesses +system.cpu.cpi 5.425421 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.425421 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2310 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34156.716418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36032.967033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2176 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4577000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.058009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3280000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039207 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039394 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency @@ -73,56 +73,56 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.226950 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.148936 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3246 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2815 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12754500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.132779 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 3235 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2804 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12765500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.133230 # miss rate for demand accesses system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 5586000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.047913 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 91.308954 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022304 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.357241 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 3235 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2815 # number of overall hits -system.cpu.dcache.overall_miss_latency 12754500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.132779 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2804 # number of overall hits +system.cpu.dcache.overall_miss_latency 12765500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.133230 # miss rate for overall accesses system.cpu.dcache.overall_misses 431 # number of overall misses system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 5586000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.047913 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.308954 # Cycle average of tags in use -system.cpu.dcache.total_refs 2852 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.357241 # Cycle average of tags in use +system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 519 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 139 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 139 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14436 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10077 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3965 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1080 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 521 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 14337 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 10064 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3903 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1073 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -133,151 +133,151 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2416 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2220 # Number of cache lines fetched -system.cpu.fetch.Cycles 6371 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 355 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15622 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 767 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085911 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2220 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.555508 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15641 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.998785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.252974 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2405 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2216 # Number of cache lines fetched +system.cpu.fetch.Cycles 6303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 358 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 15547 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 763 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085758 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2216 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.554379 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.999100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.261901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 11507 73.57% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1847 11.81% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 223 1.43% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 141 0.90% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 312 1.99% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 120 0.77% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 308 1.97% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 254 1.62% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 929 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11491 73.84% 73.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1812 11.64% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 195 1.25% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 140 0.90% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 320 2.06% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 114 0.73% 90.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 289 1.86% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 259 1.66% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 941 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15641 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35681.279621 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34902.735562 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1798 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15057500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.190090 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 15561 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35687.203791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34908.814590 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1794 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15060000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.190433 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11483000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.148198 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 11485000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.148466 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.465046 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.452888 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2220 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency -system.cpu.icache.demand_hits 1798 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15057500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.190090 # miss rate for demand accesses +system.cpu.icache.demand_accesses 2216 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency +system.cpu.icache.demand_hits 1794 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15060000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.190433 # miss rate for demand accesses system.cpu.icache.demand_misses 422 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11483000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.148198 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 11485000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.148466 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076179 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 156.015053 # Average occupied blocks per context -system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.076241 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.140617 # Average occupied blocks per context +system.cpu.icache.overall_accesses 2216 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1798 # number of overall hits -system.cpu.icache.overall_miss_latency 15057500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.190090 # miss rate for overall accesses +system.cpu.icache.overall_hits 1794 # number of overall hits +system.cpu.icache.overall_miss_latency 15060000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.190433 # miss rate for overall accesses system.cpu.icache.overall_misses 422 # number of overall misses system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11483000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.148198 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 11485000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.148466 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.015053 # Cycle average of tags in use -system.cpu.icache.total_refs 1798 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 156.140617 # Cycle average of tags in use +system.cpu.icache.total_refs 1794 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1253 # Number of branches executed -system.cpu.iew.EXEC:nop 1830 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.295249 # Inst execution rate -system.cpu.iew.EXEC:refs 3456 # number of memory reference insts executed +system.cpu.idleCycles 12483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1268 # Number of branches executed +system.cpu.iew.EXEC:nop 1827 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.295643 # Inst execution rate +system.cpu.iew.EXEC:refs 3444 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1049 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4132 # num instructions consuming a value -system.cpu.iew.WB:count 7536 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.703291 # average fanout of values written-back +system.cpu.iew.WB:consumers 4139 # num instructions consuming a value +system.cpu.iew.WB:count 7538 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704035 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2906 # num instructions producing a value -system.cpu.iew.WB:rate 0.267975 # insts written-back per cycle -system.cpu.iew.WB:sent 7618 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 681 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2914 # num instructions producing a value +system.cpu.iew.WB:rate 0.268792 # insts written-back per cycle +system.cpu.iew.WB:sent 7625 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 679 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2806 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2797 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 963 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11847 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2407 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 549 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8303 # Number of executed instructions +system.cpu.iew.iewDispatchedInsts 11802 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2395 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8291 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1080 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1073 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1642 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1633 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 409 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.183806 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.183806 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.184318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184318 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5184 58.56% 58.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2595 29.32% 87.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.02% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5173 58.55% 58.55% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2589 29.30% 87.96% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.04% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8852 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8835 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018301 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.018336 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available @@ -292,31 +292,31 @@ system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # at system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.565948 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.209939 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217819 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 11653 74.50% 74.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1757 11.23% 85.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 814 5.20% 90.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 738 4.72% 95.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 342 2.19% 97.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 199 1.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.58% 99.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.20% 99.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 11605 74.58% 74.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1745 11.21% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 791 5.08% 90.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 727 4.67% 95.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 340 2.18% 97.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 213 1.37% 99.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 93 0.60% 99.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.314771 # Inst issue rate -system.cpu.iq.iqInstsAdded 10005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8852 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.315041 # Inst issue rate +system.cpu.iq.iqInstsAdded 9963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8835 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4214 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 36 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2680 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -337,12 +337,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.221154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12953500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) @@ -364,30 +364,30 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14519500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 210.151573 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006418 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 210.308968 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses system.cpu.l2cache.overall_misses 466 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14519500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -395,27 +395,27 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 210.151573 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 210.308968 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2806 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2797 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28122 # number of cpu cycles simulated +system.cpu.numCycles 28044 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10468 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 10455 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15900 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13681 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8420 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3575 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1080 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 15765 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13587 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8333 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3513 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1073 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5010 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:UndoneMaps 4923 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 496 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 508240960..5fbc0ed64 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -359,7 +359,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 4c710c177..3ef273e4f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 13202840. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 15924344. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 85fc6bc9f..9691f5f7c 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:07 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:43:42 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:43:45 +M5 executing on zizzer command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11960500 because target called exit() +Exiting @ tick 11864500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 4d658aa1d..1e1223443 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 51828 # Simulator instruction rate (inst/s) -host_mem_usage 189300 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 106468871 # Simulator tick rate (ticks/s) +host_inst_rate 50476 # Simulator instruction rate (inst/s) +host_mem_usage 202684 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 102996710 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11960500 # Number of ticks simulated +sim_ticks 11864500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 734 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1942 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 389 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1971 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2303 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 188 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 387 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1757 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2100 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1038 # Number of branches committed system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10831 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.535500 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.248160 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 8265 76.31% 76.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1142 10.54% 86.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 659 6.08% 92.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 268 2.47% 95.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 226 2.09% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 118 1.09% 98.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 80 0.74% 99.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 22 0.20% 99.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 8225 76.26% 76.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1129 10.47% 86.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 673 6.24% 92.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 258 2.39% 95.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 226 2.10% 97.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 120 1.11% 98.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 82 0.76% 99.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 21 0.19% 99.53% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10831 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:loads 962 # Number of loads committed system.cpu.commit.COM:membars 7 # Number of memory barriers committed system.cpu.commit.COM:refs 2008 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 243 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3801 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.124483 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.124483 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1436 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33320.224719 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34437.500000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1347 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2965500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061978 # miss rate for ReadReq accesses +system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1928500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.038997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33497.150997 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35861.538462 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11757500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2331000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.048077 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2482 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33461.363636 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2042 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14723000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.177276 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4259500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.048751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016127 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.056188 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2482 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33461.363636 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2042 # number of overall hits -system.cpu.dcache.overall_miss_latency 14723000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.177276 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2050 # number of overall hits +system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses system.cpu.dcache.overall_misses 440 # number of overall misses system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4259500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.048751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.056188 # Cycle average of tags in use -system.cpu.dcache.total_refs 2085 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use +system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1201 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 148 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 256 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10901 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7556 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2000 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 615 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -134,190 +134,190 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2303 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1463 # Number of cache lines fetched -system.cpu.fetch.Cycles 3604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12241 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 411 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.096271 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1463 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 922 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.511705 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.069457 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched +system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 9306 81.30% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 148 1.29% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 183 1.60% 84.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 143 1.25% 85.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 197 1.72% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 135 1.18% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 371 3.24% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 95 0.83% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 868 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 161 1.42% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 189 1.66% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 155 1.37% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 202 1.78% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 136 1.20% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 272 2.40% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 77 0.68% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11446 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1463 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36616.094987 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34771.212121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1084 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13877500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.259057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 379 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11474500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.225564 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.284848 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.325301 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1463 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36616.094987 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency -system.cpu.icache.demand_hits 1084 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13877500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.259057 # miss rate for demand accesses -system.cpu.icache.demand_misses 379 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 49 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11474500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.225564 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses +system.cpu.icache.demand_misses 386 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077734 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 159.198376 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1463 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36616.094987 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1084 # number of overall hits -system.cpu.icache.overall_miss_latency 13877500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.259057 # miss rate for overall accesses -system.cpu.icache.overall_misses 379 # number of overall misses -system.cpu.icache.overall_mshr_hits 49 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11474500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.225564 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses +system.cpu.icache.overall_hits 1104 # number of overall hits +system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses +system.cpu.icache.overall_misses 386 # number of overall misses +system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 159.198376 # Cycle average of tags in use -system.cpu.icache.total_refs 1084 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use +system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12476 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1260 # Number of branches executed +system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1261 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.324680 # Inst execution rate -system.cpu.iew.EXEC:refs 2768 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1280 # Number of stores executed +system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate +system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1315 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5977 # num instructions consuming a value -system.cpu.iew.WB:count 7563 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.643801 # average fanout of values written-back +system.cpu.iew.WB:consumers 5889 # num instructions consuming a value +system.cpu.iew.WB:count 7582 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3848 # num instructions producing a value -system.cpu.iew.WB:rate 0.316152 # insts written-back per cycle -system.cpu.iew.WB:sent 7622 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1815 # Number of dispatched load instructions +system.cpu.iew.WB:producers 3806 # num instructions producing a value +system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle +system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1394 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9586 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 320 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7767 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9185 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7791 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 615 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 42 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 853 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 348 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 64 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.242455 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.242455 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 719 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 404 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5153 63.72% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1611 19.92% 83.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1321 16.33% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8087 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017435 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8089 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 153 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018915 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.80% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 67 47.52% 55.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 63 44.68% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.19% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11446 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.706535 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384911 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 8157 71.27% 71.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1172 10.24% 81.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 822 7.18% 88.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 530 4.63% 93.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 377 3.29% 96.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 216 1.89% 98.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 120 1.05% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 43 0.38% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 8066 71.03% 71.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1182 10.41% 81.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 820 7.22% 88.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 507 4.46% 93.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 388 3.42% 96.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 218 1.92% 98.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 121 1.07% 99.53% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 46 0.41% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11446 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.338057 # Inst issue rate -system.cpu.iq.iqInstsAdded 9564 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8087 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate +system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3408 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2985 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3586 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -328,28 +328,28 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34697.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1512000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.084656 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12978000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.979275 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 378 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11777000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34235.294118 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 582000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles @@ -357,69 +357,69 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.022161 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34374.413146 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981567 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 426 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13289000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13361000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981651 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 180.652204 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34374.413146 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981567 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 426 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13289000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 426 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13361000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981651 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 428 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 361 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 180.652204 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1815 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1394 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23922 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 356 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 23730 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7745 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 222 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 17199 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10376 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 9321 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1877 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 615 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 273 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4314 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 580 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 571 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls |