diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
| commit | 62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch) | |
| tree | 739253709735d1a8b5da963d2230a5418779d297 /tests/quick/00.hello/ref | |
| parent | b179c3f4cd1e89872de34d70105f703e72377029 (diff) | |
| download | gem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz | |
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'tests/quick/00.hello/ref')
24 files changed, 803 insertions, 797 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index f857ba9ca..80cb33a4e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index dd4839763..684f7196b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 665 # Number of BTB hits -global.BPredUnit.BTBLookups 1852 # Number of BTB lookups +global.BPredUnit.BTBHits 649 # Number of BTB hits +global.BPredUnit.BTBLookups 1748 # Number of BTB lookups global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 424 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1300 # Number of conditional branches predicted -global.BPredUnit.lookups 2168 # Number of BP lookups -global.BPredUnit.usedRAS 288 # Number of times the RAS was used to get a target. -host_inst_rate 54768 # Simulator instruction rate (inst/s) -host_mem_usage 209744 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 47820234 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 35 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 112 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2210 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1280 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted +global.BPredUnit.lookups 2108 # Number of BP lookups +global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target. +host_inst_rate 87257 # Simulator instruction rate (inst/s) +host_mem_usage 198272 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 171219532 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 28 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6297 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5506500 # Number of ticks simulated +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12391500 # Number of ticks simulated system.cpu.commit.COM:branches 1012 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 113 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9764 +system.cpu.commit.COM:committed_per_cycle.samples 12114 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7128 7300.29% - 1 1385 1418.48% - 2 452 462.93% - 3 225 230.44% - 4 157 160.79% - 5 102 104.47% - 6 106 108.56% - 7 96 98.32% - 8 113 115.73% + 0 9249 7634.97% + 1 1607 1326.56% + 2 479 395.41% + 3 271 223.71% + 4 137 113.09% + 5 121 99.88% + 6 87 71.82% + 7 43 35.50% + 8 120 99.06% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 1168 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 352 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4192 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit system.cpu.committedInsts 6297 # Number of Instructions Simulated system.cpu.committedInsts_total 6297 # Number of Instructions Simulated -system.cpu.cpi 1.749087 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.749087 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10996.240602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8551.020408 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1625 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1462500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.075654 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 838000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.055745 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses +system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8662.162162 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7459.770115 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 492 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3205000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.429234 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 370 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 649000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.605882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2620 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9279.324056 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2117 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4667500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.191985 # miss rate for demand accesses -system.cpu.dcache.demand_misses 503 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 318 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070611 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses +system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2620 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9279.324056 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2117 # number of overall hits -system.cpu.dcache.overall_miss_latency 4667500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.191985 # miss rate for overall accesses -system.cpu.dcache.overall_misses 503 # number of overall misses -system.cpu.dcache.overall_mshr_hits 318 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1487000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070611 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2058 # number of overall hits +system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses +system.cpu.dcache.overall_misses 542 # number of overall misses +system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,103 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 109.392910 # Cycle average of tags in use -system.cpu.dcache.total_refs 2143 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use +system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 170 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12212 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7007 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2262 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 791 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 224 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2901 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 2892 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2837 # DTB hits -system.cpu.dtb.misses 64 # DTB misses -system.cpu.dtb.read_accesses 1842 # DTB read accesses +system.cpu.dtb.hits 2831 # DTB hits +system.cpu.dtb.misses 61 # DTB misses +system.cpu.dtb.read_accesses 1821 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1799 # DTB read hits -system.cpu.dtb.read_misses 43 # DTB read misses -system.cpu.dtb.write_accesses 1059 # DTB write accesses +system.cpu.dtb.read_hits 1785 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.write_accesses 1071 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1038 # DTB write hits -system.cpu.dtb.write_misses 21 # DTB write misses -system.cpu.fetch.Branches 2168 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1670 # Number of cache lines fetched -system.cpu.fetch.Cycles 4064 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.196840 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 953 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.196386 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 1046 # DTB write hits +system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched +system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10556 +system.cpu.fetch.rateDist.samples 12970 system.cpu.fetch.rateDist.min_value 0 - 0 8192 7760.52% - 1 236 223.57% - 2 214 202.73% - 3 172 162.94% - 4 242 229.25% - 5 149 141.15% - 6 203 192.31% - 7 118 111.78% - 8 1030 975.75% + 0 10663 8221.28% + 1 241 185.81% + 2 214 165.00% + 3 169 130.30% + 4 208 160.37% + 5 163 125.67% + 6 215 165.77% + 7 128 98.69% + 8 969 747.11% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1670 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9198.550725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6610.932476 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1325 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3173500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206587 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2056000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.186228 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.260450 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1670 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9198.550725 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency -system.cpu.icache.demand_hits 1325 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3173500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206587 # miss rate for demand accesses -system.cpu.icache.demand_misses 345 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2056000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.186228 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency +system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses +system.cpu.icache.demand_misses 426 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1670 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9198.550725 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1325 # number of overall hits -system.cpu.icache.overall_miss_latency 3173500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206587 # miss rate for overall accesses -system.cpu.icache.overall_misses 345 # number of overall misses -system.cpu.icache.overall_mshr_hits 34 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2056000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.186228 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses +system.cpu.icache.overall_hits 1278 # number of overall hits +system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses +system.cpu.icache.overall_misses 426 # number of overall misses +system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 166.219676 # Cycle average of tags in use -system.cpu.icache.total_refs 1325 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use +system.cpu.icache.total_refs 1278 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 458 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1365 # Number of branches executed -system.cpu.iew.EXEC:nop 69 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.792628 # Inst execution rate -system.cpu.iew.EXEC:refs 2907 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1061 # Number of stores executed +system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1375 # Number of branches executed +system.cpu.iew.EXEC:nop 76 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate +system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1073 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5886 # num instructions consuming a value -system.cpu.iew.WB:count 8407 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745158 # average fanout of values written-back +system.cpu.iew.WB:consumers 5878 # num instructions consuming a value +system.cpu.iew.WB:count 8512 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4386 # num instructions producing a value -system.cpu.iew.WB:rate 0.763301 # insts written-back per cycle -system.cpu.iew.WB:sent 8526 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 417 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2210 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1280 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10601 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8730 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4396 # num instructions producing a value +system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle +system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 40 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1042 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.571727 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.571727 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9083 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 6020 66.28% # Type of FU issued + IntAlu 6072 66.72% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1973 21.72% # Type of FU issued - MemWrite 1085 11.95% # Type of FU issued + MemRead 1928 21.18% # Type of FU issued + MemWrite 1096 12.04% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 107 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011780 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 0.93% # attempts to use FU when none available + IntAlu 2 2.15% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,100 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 72 67.29% # attempts to use FU when none available - MemWrite 34 31.78% # attempts to use FU when none available + MemRead 56 60.22% # attempts to use FU when none available + MemWrite 35 37.63% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10556 +system.cpu.iq.ISSUE:issued_per_cycle.samples 12970 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6842 6481.62% - 1 1288 1220.16% - 2 888 841.23% - 3 723 684.92% - 4 456 431.98% - 5 198 187.57% - 6 106 100.42% - 7 40 37.89% - 8 15 14.21% + 0 8890 6854.28% + 1 1667 1285.27% + 2 1037 799.54% + 3 696 536.62% + 4 340 262.14% + 5 189 145.72% + 6 103 79.41% + 7 35 26.99% + 8 13 10.02% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.824678 # Inst issue rate -system.cpu.iq.iqInstsAdded 10508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9083 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3829 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2415 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1700 # ITB accesses +system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate +system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1737 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1670 # ITB hits -system.cpu.itb.misses 30 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 440000 # number of ReadExReq miss cycles +system.cpu.itb.hits 1704 # ITB hits +system.cpu.itb.misses 33 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5746.323529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2746.323529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2344500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997555 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 408 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1120500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 408 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5633.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2633.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 84500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 39500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5801.041667 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2784500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1344500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5801.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2784500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 480 # number of overall misses +system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 479 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1344500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -415,29 +415,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 220.053695 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 11014 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking +system.cpu.numCycles 24784 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 7177 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14809 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11658 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8660 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2106 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 791 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4123 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 80 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 5992f7131..337694eda 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 2c5a26de6..d863a4704 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 15:48:11 -M5 started Wed Jul 23 15:48:39 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:08:49 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 5506500 because target called exit() +Exiting @ tick 12391500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 43431aef9..1ee191af5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 22e685732..7935839f7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 65172 # Simulator instruction rate (inst/s) -host_mem_usage 209040 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 208535003 # Simulator tick rate (ticks/s) +host_inst_rate 496189 # Simulator instruction rate (inst/s) +host_mem_usage 197472 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2580329636 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6315 # Number of instructions simulated -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20250000 # Number of ticks simulated +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33503000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5152000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4876000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10024000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9487000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1851 # number of overall hits -system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10024000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses system.cpu.dcache.overall_misses 179 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9487000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 104.470522 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.087516 # Cycle average of tags in use system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26953.405018 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.405018 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26953.405018 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses system.cpu.icache.demand_misses 279 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26953.405018 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6047 # number of overall hits -system.cpu.icache.overall_miss_latency 7520000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses system.cpu.icache.overall_misses 279 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.005587 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.637082 # Cycle average of tags in use system.cpu.icache.total_refs 6047 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 6326 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1679000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19240000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 14800000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -196,29 +196,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10189000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23036000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4873000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17720000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10189000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23036000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses system.cpu.l2cache.overall_misses 443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4873000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17720000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -235,12 +235,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 183.192305 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.910312 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 40500 # number of cpu cycles simulated +system.cpu.numCycles 67006 # number of cpu cycles simulated system.cpu.num_insts 6315 # Number of instructions executed system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr index 5992f7131..598fc86c0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index a4ec269db..90b25945e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 15:48:11 -M5 started Wed Jul 23 15:50:09 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:10:34 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 20250000 because target called exit() +Exiting @ tick 33503000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 2971dacfa..a04865714 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index b9f64c44d..110788930 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 155 # Number of BTB hits -global.BPredUnit.BTBLookups 639 # Number of BTB lookups -global.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +global.BPredUnit.BTBHits 198 # Number of BTB hits +global.BPredUnit.BTBLookups 684 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 405 # Number of conditional branches predicted -global.BPredUnit.lookups 821 # Number of BP lookups -global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. -host_inst_rate 39438 # Simulator instruction rate (inst/s) -host_mem_usage 151264 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 44410086 # Simulator tick rate (ticks/s) +global.BPredUnit.condPredicted 447 # Number of conditional branches predicted +global.BPredUnit.lookups 859 # Number of BP lookups +global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. +host_inst_rate 67408 # Simulator instruction rate (inst/s) +host_mem_usage 197188 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 201701674 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 408 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2700000 # Number of ticks simulated +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 7183000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 4866 +system.cpu.commit.COM:committed_per_cycle.samples 6196 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3922 8060.01% - 1 255 524.04% - 2 327 672.01% - 3 133 273.33% - 4 67 137.69% - 5 70 143.86% - 6 33 67.82% - 7 20 41.10% - 8 39 80.15% + 0 5239 8455.46% + 1 263 424.47% + 2 334 539.06% + 3 134 216.27% + 4 73 117.82% + 5 63 101.68% + 6 32 51.65% + 7 20 32.28% + 8 38 61.33% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1414 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 542 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9881.944444 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.132841 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.112546 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9732.673267 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.343537 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 836 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9794.797688 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency -system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.206938 # miss rate for demand accesses -system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.117225 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses +system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 836 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9794.797688 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 663 # number of overall hits -system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.206938 # miss rate for overall accesses -system.cpu.dcache.overall_misses 173 # number of overall misses -system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.117225 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 674 # number of overall hits +system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses +system.cpu.dcache.overall_misses 193 # number of overall misses +system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use -system.cpu.dcache.total_refs 694 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use +system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 133 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4610 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3877 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 889 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 290 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 293 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 936 # DTB accesses +system.cpu.dtb.accesses 971 # DTB accesses system.cpu.dtb.acv 1 # DTB access violations -system.cpu.dtb.hits 911 # DTB hits +system.cpu.dtb.hits 946 # DTB hits system.cpu.dtb.misses 25 # DTB misses -system.cpu.dtb.read_accesses 578 # DTB read accesses +system.cpu.dtb.read_accesses 611 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 567 # DTB read hits +system.cpu.dtb.read_hits 600 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 358 # DTB write accesses +system.cpu.dtb.write_accesses 360 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 344 # DTB write hits +system.cpu.dtb.write_hits 346 # DTB write hits system.cpu.dtb.write_misses 14 # DTB write misses -system.cpu.fetch.Branches 821 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 705 # Number of cache lines fetched -system.cpu.fetch.Cycles 1625 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 104 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5290 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 238 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.152009 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 705 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 317 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.979448 # Number of inst fetches per cycle +system.cpu.fetch.Branches 859 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 747 # Number of cache lines fetched +system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 5157 +system.cpu.fetch.rateDist.samples 6528 system.cpu.fetch.rateDist.min_value 0 - 0 4266 8272.25% - 1 34 65.93% - 2 85 164.82% - 3 67 129.92% - 4 115 223.00% - 5 55 106.65% - 6 41 79.50% - 7 48 93.08% - 8 446 864.84% + 0 5595 8570.77% + 1 36 55.15% + 2 100 153.19% + 3 69 105.70% + 4 130 199.14% + 5 72 110.29% + 6 45 68.93% + 7 48 73.53% + 8 433 663.30% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 705 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8914.634146 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.290780 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 205 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.258156 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.747253 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 705 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8914.634146 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency -system.cpu.icache.demand_hits 500 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.290780 # miss rate for demand accesses -system.cpu.icache.demand_misses 205 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.258156 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.demand_hits 512 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses +system.cpu.icache.demand_misses 235 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 705 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8914.634146 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency +system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 500 # number of overall hits -system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.290780 # miss rate for overall accesses -system.cpu.icache.overall_misses 205 # number of overall misses -system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.258156 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.icache.overall_hits 512 # number of overall hits +system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses +system.cpu.icache.overall_misses 235 # number of overall misses +system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 91.765219 # Cycle average of tags in use -system.cpu.icache.total_refs 500 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use +system.cpu.icache.total_refs 512 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 542 # Number of branches executed -system.cpu.iew.EXEC:nop 277 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.591187 # Inst execution rate -system.cpu.iew.EXEC:refs 939 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 358 # Number of stores executed +system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 584 # Number of branches executed +system.cpu.iew.EXEC:nop 286 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate +system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 360 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1788 # num instructions consuming a value -system.cpu.iew.WB:count 3104 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back +system.cpu.iew.WB:consumers 1896 # num instructions consuming a value +system.cpu.iew.WB:count 3311 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1414 # num instructions producing a value -system.cpu.iew.WB:rate 0.574708 # insts written-back per cycle -system.cpu.iew.WB:sent 3141 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 150 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 703 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1509 # num instructions producing a value +system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle +system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 408 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4070 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 581 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 98 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3193 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 290 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 288 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 114 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.441955 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.441955 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3291 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 2327 70.71% # Type of FU issued + IntAlu 2506 71.31% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 599 18.20% # Type of FU issued - MemWrite 364 11.06% # Type of FU issued + MemRead 639 18.18% # Type of FU issued + MemWrite 368 10.47% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010635 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 2.86% # attempts to use FU when none available + IntAlu 1 2.94% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,63 +309,63 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 12 34.29% # attempts to use FU when none available - MemWrite 22 62.86% # attempts to use FU when none available + MemRead 11 32.35% # attempts to use FU when none available + MemWrite 22 64.71% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 5157 +system.cpu.iq.ISSUE:issued_per_cycle.samples 6528 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3776 7322.09% - 1 540 1047.12% - 2 304 589.49% - 3 226 438.24% - 4 166 321.89% - 5 89 172.58% - 6 40 77.56% - 7 12 23.27% - 8 4 7.76% + 0 5051 7737.44% + 1 569 871.63% + 2 331 507.05% + 3 253 387.56% + 4 172 263.48% + 5 97 148.59% + 6 39 59.74% + 7 11 16.85% + 8 5 7.66% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.609332 # Inst issue rate -system.cpu.iq.iqInstsAdded 3787 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3291 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate +system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 732 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 734 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 776 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 705 # ITB hits +system.cpu.itb.hits 747 # ITB hits system.cpu.itb.misses 29 # ITB misses system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5854.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2854.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 140500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5440.329218 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2440.329218 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1322000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 593000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5571.428571 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2571.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 78000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -376,32 +376,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5477.528090 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1462500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5477.528090 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1462500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 267 # number of overall misses +system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 661500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -414,28 +414,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 114.387820 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 5401 # number of cpu cycles simulated +system.cpu.numCycles 14367 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3954 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5025 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4444 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3187 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 813 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 290 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1419 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 91 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 46 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index 298b6fba0..19df33f11 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index abedce50c..c1c2d8a89 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:59 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:08:50 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 2700000 because target called exit() +Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 7d543f47c..d146bb3c1 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index c93b1f19c..ae6876b28 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 99969 # Simulator instruction rate (inst/s) -host_mem_usage 193012 # Number of bytes of host memory used +host_inst_rate 96492 # Simulator instruction rate (inst/s) +host_mem_usage 196528 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 383001655 # Simulator tick rate (ticks/s) +host_tick_rate 644436202 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 9950000 # Number of ticks simulated +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17374000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses system.cpu.dcache.overall_misses 93 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,30 +160,30 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 2586 # ITB hits system.cpu.itb.misses 11 # ITB misses system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -195,29 +195,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 19900 # number of cpu cycles simulated +system.cpu.numCycles 34748 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index f26dcb93f..bc68d7b07 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index d1bbc80b8..97ac18bed 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:24:22 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:25 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 9950000 because target called exit() +Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index e5f76a0a8..fa2de5431 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -226,6 +226,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 @@ -251,7 +252,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index d3bab9d0b..c07fb7a13 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11117 # Simulator instruction rate (inst/s) -host_mem_usage 195308 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host -host_tick_rate 38035865 # Simulator tick rate (ticks/s) +host_inst_rate 142745 # Simulator instruction rate (inst/s) +host_mem_usage 198836 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 810420480 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19359000 # Number of ticks simulated +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 32322000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1968000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1728000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3942000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1908 # number of overall hits -system.cpu.dcache.overall_miss_latency 3942000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses system.cpu.dcache.overall_misses 146 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3504000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.621729 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -90,13 +90,13 @@ system.cpu.dtb.write_accesses 0 # DT system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26914.191419 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23914.191419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8155000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 7246000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -108,29 +108,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26914.191419 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8155000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 7246000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26914.191419 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 8155000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 7246000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -147,7 +147,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.855992 # Cycle average of tags in use +system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -162,31 +162,31 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8809000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9959000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9959000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 183.190154 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 38718 # number of cpu cycles simulated +system.cpu.numCycles 64644 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.tlb.accesses 0 # DTB accesses diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr index 5992f7131..1ad466eb8 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 37be8fb0c..4c9c838f5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:31:07 -M5 started Mon Jul 21 20:31:09 2008 +M5 compiled Aug 2 2008 17:07:38 +M5 started Sat Aug 2 17:07:42 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello World! -Exiting @ tick 19359000 because target called exit() +Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 834e9fbf3..1194cf323 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 132891c92..39cffe2aa 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 56962 # Simulator instruction rate (inst/s) -host_mem_usage 210220 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 184294275 # Simulator tick rate (ticks/s) +host_inst_rate 288337 # Simulator instruction rate (inst/s) +host_mem_usage 198672 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1546587822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17315000 # Number of ticks simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29031000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1239 # number of overall hits -system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5127 # number of overall hits -system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,37 +138,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use +system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -180,29 +180,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 34630 # number of cpu cycles simulated +system.cpu.numCycles 58062 # number of cpu cycles simulated system.cpu.num_insts 5340 # Number of instructions executed system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr index 2a6ac4135..320065be7 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 9fab97574..85eaa5038 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:00:56 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:29:40 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 17315000 because target called exit() +Hello World!Exiting @ tick 29031000 because target called exit() |