diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2008-11-09 21:57:15 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2008-11-09 21:57:15 -0800 |
commit | c981b7ed50167a9598f6f8773ab78b47b81aa08a (patch) | |
tree | e176a3111dc98dc7e3414c40724653c097606f8b /tests/quick/00.hello/ref | |
parent | 846cb450f985eb249a5fc50e97f9e643cb1ebfc5 (diff) | |
download | gem5-c981b7ed50167a9598f6f8773ab78b47b81aa08a.tar.xz |
X86: Add x86 reference output for the timing CPU.
Diffstat (limited to 'tests/quick/00.hello/ref')
4 files changed, 446 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..6b3961ac8 --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..cb9de2cde --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt @@ -0,0 +1,232 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 106773 # Simulator instruction rate (inst/s) +host_mem_usage 197592 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 379942758 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 9493 # Number of instructions simulated +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33851000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses +system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1835 # number of overall hits +system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses +system.cpu.dcache.overall_misses 152 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use +system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses +system.cpu.icache.demand_misses 228 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 10779 # number of overall hits +system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses +system.cpu.icache.overall_misses 228 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use +system.cpu.icache.total_refs 10779 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 360 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 67702 # number of cpu cycles simulated +system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.num_refs 2003 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr b/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr new file mode 100755 index 000000000..72ba90ece --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stderr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout b/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout new file mode 100755 index 000000000..9c811f04f --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stdout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 00:19:20 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 33851000 because target called exit() |