diff options
| author | Nathan Binkert <nate@binkert.org> | 2008-07-24 16:31:54 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-07-24 16:31:54 -0700 |
| commit | 0622eec53ae87e008a8d5e0e685321c69ea401d3 (patch) | |
| tree | a11ed967728a45a162e601263db3c161fe3ec82d /tests/quick/00.hello/ref | |
| parent | f3a3ab7f2cfdae687a1dc07dff10c7fa4bde921c (diff) | |
| download | gem5-0622eec53ae87e008a8d5e0e685321c69ea401d3.tar.xz | |
regress: update regressions for tty emulation fix.
Diffstat (limited to 'tests/quick/00.hello/ref')
18 files changed, 509 insertions, 503 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 3db01031d..f857ba9ca 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index cd104d2c8..dd4839763 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 574 # Number of BTB hits -global.BPredUnit.BTBLookups 1715 # Number of BTB lookups -global.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 425 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted -global.BPredUnit.lookups 2013 # Number of BP lookups -global.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. -host_inst_rate 44727 # Simulator instruction rate (inst/s) -host_mem_usage 151980 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 42091644 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1228 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 665 # Number of BTB hits +global.BPredUnit.BTBLookups 1852 # Number of BTB lookups +global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 424 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1300 # Number of conditional branches predicted +global.BPredUnit.lookups 2168 # Number of BP lookups +global.BPredUnit.usedRAS 288 # Number of times the RAS was used to get a target. +host_inst_rate 54768 # Simulator instruction rate (inst/s) +host_mem_usage 209744 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 47820234 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 35 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 112 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2210 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1280 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5303000 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 89 # number cycles where commit BW limit reached +sim_insts 6297 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5506500 # Number of ticks simulated +system.cpu.commit.COM:branches 1012 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9365 +system.cpu.commit.COM:committed_per_cycle.samples 9764 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7035 7512.01% - 1 1204 1285.64% - 2 411 438.87% - 3 192 205.02% - 4 145 154.83% - 5 90 96.10% - 6 97 103.58% - 7 102 108.92% - 8 89 95.03% + 0 7128 7300.29% + 1 1385 1418.48% + 2 452 462.93% + 3 225 230.44% + 4 157 160.79% + 5 102 104.47% + 6 106 108.56% + 7 96 98.32% + 8 113 115.73% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:count 6314 # Number of instructions committed +system.cpu.commit.COM:loads 1168 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 353 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.branchMispredicts 352 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4190 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.886360 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.886360 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1566 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10875.939850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8494.897959 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1433 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.084930 # miss rate for ReadReq accesses +system.cpu.commit.commitSquashedInsts 4192 # The number of squashed insts skipped by commit +system.cpu.committedInsts 6297 # Number of Instructions Simulated +system.cpu.committedInsts_total 6297 # Number of Instructions Simulated +system.cpu.cpi 1.749087 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.749087 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10996.240602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8551.020408 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1625 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1462500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075654 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 832500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.055745 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8648.247978 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7436.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 441 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3208500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.456897 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 371 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 8662.162162 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7459.770115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 492 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3205000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.429234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 370 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 649000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.188235 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.605882 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2378 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1874 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4655000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.211943 # miss rate for demand accesses -system.cpu.dcache.demand_misses 504 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1479500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.077796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2620 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9279.324056 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2117 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4667500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.191985 # miss rate for demand accesses +system.cpu.dcache.demand_misses 503 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 318 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.070611 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2378 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2620 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9279.324056 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1874 # number of overall hits -system.cpu.dcache.overall_miss_latency 4655000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.211943 # miss rate for overall accesses -system.cpu.dcache.overall_misses 504 # number of overall misses -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1479500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.077796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2117 # number of overall hits +system.cpu.dcache.overall_miss_latency 4667500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.191985 # miss rate for overall accesses +system.cpu.dcache.overall_misses 503 # number of overall misses +system.cpu.dcache.overall_mshr_hits 318 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.070611 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 107.937594 # Cycle average of tags in use -system.cpu.dcache.total_refs 1902 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.392910 # Cycle average of tags in use +system.cpu.dcache.total_refs 2143 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 163 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11516 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6794 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2076 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 792 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 231 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BranchResolved 170 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12212 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7007 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2262 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 791 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 224 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2663 # DTB accesses +system.cpu.dtb.accesses 2901 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2604 # DTB hits -system.cpu.dtb.misses 59 # DTB misses -system.cpu.dtb.read_accesses 1652 # DTB read accesses +system.cpu.dtb.hits 2837 # DTB hits +system.cpu.dtb.misses 64 # DTB misses +system.cpu.dtb.read_accesses 1842 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1614 # DTB read hits -system.cpu.dtb.read_misses 38 # DTB read misses -system.cpu.dtb.write_accesses 1011 # DTB write accesses +system.cpu.dtb.read_hits 1799 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses +system.cpu.dtb.write_accesses 1059 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 990 # DTB write hits +system.cpu.dtb.write_hits 1038 # DTB write hits system.cpu.dtb.write_misses 21 # DTB write misses -system.cpu.fetch.Branches 2013 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1565 # Number of cache lines fetched -system.cpu.fetch.Cycles 3769 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 233 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12458 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2168 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1670 # Number of cache lines fetched +system.cpu.fetch.Cycles 4064 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.189780 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 844 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.174507 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.196840 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 953 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.196386 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10158 +system.cpu.fetch.rateDist.samples 10556 system.cpu.fetch.rateDist.min_value 0 - 0 7986 7861.78% - 1 184 181.14% - 2 171 168.34% - 3 148 145.70% - 4 221 217.56% - 5 166 163.42% - 6 188 185.08% - 7 106 104.35% - 8 988 972.63% + 0 8192 7760.52% + 1 236 223.57% + 2 214 202.73% + 3 172 162.94% + 4 242 229.25% + 5 149 141.15% + 6 203 192.31% + 7 118 111.78% + 8 1030 975.75% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9178.260870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6606.451613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1220 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.220447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9198.550725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6610.932476 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1325 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3173500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206587 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2048000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.198083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.186228 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.935484 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.260450 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1565 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1220 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.220447 # miss rate for demand accesses +system.cpu.icache.demand_accesses 1670 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9198.550725 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency +system.cpu.icache.demand_hits 1325 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3173500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206587 # miss rate for demand accesses system.cpu.icache.demand_misses 345 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2048000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.198083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.186228 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1565 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1670 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9198.550725 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1220 # number of overall hits -system.cpu.icache.overall_miss_latency 3166500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.220447 # miss rate for overall accesses +system.cpu.icache.overall_hits 1325 # number of overall hits +system.cpu.icache.overall_miss_latency 3173500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206587 # miss rate for overall accesses system.cpu.icache.overall_misses 345 # number of overall misses -system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2048000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.198083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_mshr_hits 34 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2056000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.186228 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 162.483905 # Cycle average of tags in use -system.cpu.icache.total_refs 1220 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 166.219676 # Cycle average of tags in use +system.cpu.icache.total_refs 1325 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 449 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1210 # Number of branches executed -system.cpu.iew.EXEC:nop 70 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.759310 # Inst execution rate -system.cpu.iew.EXEC:refs 2668 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1014 # Number of stores executed +system.cpu.idleCycles 458 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1365 # Number of branches executed +system.cpu.iew.EXEC:nop 69 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.792628 # Inst execution rate +system.cpu.iew.EXEC:refs 2907 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1061 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5427 # num instructions consuming a value -system.cpu.iew.WB:count 7728 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.742583 # average fanout of values written-back +system.cpu.iew.WB:consumers 5886 # num instructions consuming a value +system.cpu.iew.WB:count 8407 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745158 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4030 # num instructions producing a value -system.cpu.iew.WB:rate 0.728575 # insts written-back per cycle -system.cpu.iew.WB:sent 7840 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 420 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 4386 # num instructions producing a value +system.cpu.iew.WB:rate 0.763301 # insts written-back per cycle +system.cpu.iew.WB:sent 8526 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 417 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2210 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 185 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1228 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9927 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8054 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1280 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10601 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1846 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8730 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 792 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 40 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1034 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 416 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1042 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.530122 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.530122 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8404 # Type of FU issued +system.cpu.ipc 0.571727 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.571727 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9083 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5587 66.48% # Type of FU issued + IntAlu 6020 66.28% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1774 21.11% # Type of FU issued - MemWrite 1038 12.35% # Type of FU issued + MemRead 1973 21.72% # Type of FU issued + MemWrite 1085 11.95% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 103 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012256 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 107 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011780 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 0.97% # attempts to use FU when none available + IntAlu 1 0.93% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,38 +309,38 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 68 66.02% # attempts to use FU when none available - MemWrite 34 33.01% # attempts to use FU when none available + MemRead 72 67.29% # attempts to use FU when none available + MemWrite 34 31.78% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10158 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10556 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6739 6634.18% - 1 1163 1144.91% - 2 838 824.97% - 3 636 626.11% - 4 450 443.00% - 5 195 191.97% - 6 92 90.57% - 7 30 29.53% - 8 15 14.77% + 0 6842 6481.62% + 1 1288 1220.16% + 2 888 841.23% + 3 723 684.92% + 4 456 431.98% + 5 198 187.57% + 6 106 100.42% + 7 40 37.89% + 8 15 14.21% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.792307 # Inst issue rate -system.cpu.iq.iqInstsAdded 9833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8404 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.824678 # Inst issue rate +system.cpu.iq.iqInstsAdded 10508 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9083 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3830 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3829 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2411 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1597 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 2415 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1700 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1565 # ITB hits -system.cpu.itb.misses 32 # ITB misses +system.cpu.itb.hits 1670 # ITB hits +system.cpu.itb.misses 30 # ITB misses system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency @@ -350,59 +350,59 @@ system.cpu.l2cache.ReadExReq_misses 72 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5733.415233 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2733.415233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5746.323529 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2746.323529 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1112500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2344500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997555 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 408 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1120500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997555 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 408 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5433.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2433.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 81500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5633.333333 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2633.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 84500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 39500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5801.041667 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2784500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1336500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1344500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5801.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2773500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 479 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2784500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1336500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1344500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -415,29 +415,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 215.878593 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.053695 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 10607 # number of cpu cycles simulated +system.cpu.numCycles 11014 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 6962 # Number of cycles rename is idle +system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 7177 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14001 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10976 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8169 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 792 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 14809 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11658 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8660 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2106 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 791 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4118 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 4123 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 79 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 80 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 05d3c33eb..2c5a26de6 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:18:02 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:48:39 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 5303000 because target called exit() +Exiting @ tick 5506500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index e68e8bc1c..5214649cb 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index c89057e77..6f4810c44 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 274181 # Simulator instruction rate (inst/s) -host_mem_usage 172576 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 135418658 # Simulator tick rate (ticks/s) +host_inst_rate 74368 # Simulator instruction rate (inst/s) +host_mem_usage 201628 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 37260110 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated +sim_insts 6315 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2833500 # Number of ticks simulated -system.cpu.dtb.accesses 1801 # DTB accesses +sim_ticks 3170500 # Number of ticks simulated +system.cpu.dtb.accesses 2040 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2030 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1175 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1168 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 865 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.accesses 6342 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.hits 6325 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5668 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 6342 # number of cpu cycles simulated +system.cpu.num_insts 6315 # Number of instructions executed +system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index ae7c0fe57..7e1e7de26 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:07 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:50:09 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 2833500 because target called exit() +Exiting @ tick 3170500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index bbb328185..43431aef9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index d791e0a2e..22e685732 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11324 # Simulator instruction rate (inst/s) -host_mem_usage 193960 # Number of bytes of host memory used -host_seconds 0.50 # Real time elapsed on the host -host_tick_rate 38693743 # Simulator tick rate (ticks/s) +host_inst_rate 65172 # Simulator instruction rate (inst/s) +host_mem_usage 209040 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 208535003 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19285000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) +sim_insts 6315 # Number of instructions simulated +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20250000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.303030 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1612 # number of overall hits +system.cpu.dcache.overall_hits 1851 # number of overall hits system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses system.cpu.dcache.overall_misses 179 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -76,66 +76,66 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.207107 # Cycle average of tags in use -system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 104.470522 # Cycle average of tags in use +system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.accesses 2040 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2030 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1175 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1168 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 865 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26953.068592 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.068592 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7466000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26953.405018 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.405018 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 21.673835 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency -system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7466000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses -system.cpu.icache.demand_misses 277 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26953.405018 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency +system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses +system.cpu.icache.demand_misses 279 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency +system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26953.405018 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5375 # number of overall hits -system.cpu.icache.overall_miss_latency 7466000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses -system.cpu.icache.overall_misses 277 # number of overall misses +system.cpu.icache.overall_hits 6047 # number of overall hits +system.cpu.icache.overall_miss_latency 7520000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses +system.cpu.icache.overall_misses 279 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -148,16 +148,16 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 127.893604 # Cycle average of tags in use -system.cpu.icache.total_refs 5375 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 133.005587 # Cycle average of tags in use +system.cpu.icache.total_refs 6047 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5669 # ITB accesses +system.cpu.itb.accesses 6343 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5652 # ITB hits +system.cpu.itb.hits 6326 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 73 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8464000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 8510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -189,38 +189,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002825 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002809 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10143000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 10189000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4873000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10143000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 441 # number of overall misses +system.cpu.l2cache.overall_miss_latency 10189000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4873000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -233,16 +233,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 177.260989 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.192305 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 38570 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 40500 # number of cpu cycles simulated +system.cpu.num_insts 6315 # Number of instructions executed +system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index c8cf5ab9d..a4ec269db 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:14:04 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:50:09 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 19285000 because target called exit() +Exiting @ tick 20250000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index d13eeb4e2..a80c5cabd 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 9a9ac5a12..c2853cc3f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1230 # Simulator instruction rate (inst/s) -host_mem_usage 173824 # Number of bytes of host memory used -host_seconds 3.93 # Real time elapsed on the host -host_tick_rate 622698 # Simulator tick rate (ticks/s) +host_inst_rate 31798 # Simulator instruction rate (inst/s) +host_mem_usage 202884 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 16065810 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2447500 # Number of ticks simulated +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2701000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4896 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index b07b710c8..c0e107ab6 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:55 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 2447500 because target called exit() +Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 092061e7f..834e9fbf3 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 08e810a08..132891c92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153074 # Simulator instruction rate (inst/s) -host_mem_usage 195092 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 524572616 # Simulator tick rate (ticks/s) +host_inst_rate 56962 # Simulator instruction rate (inst/s) +host_mem_usage 210220 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 184294275 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated +sim_insts 5340 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16662000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) +sim_ticks 17315000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 565 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.145234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.145234 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.400000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1119 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.118203 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1119 # number of overall hits +system.cpu.dcache.overall_hits 1239 # number of overall hits system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.118203 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.706581 # Cycle average of tags in use -system.cpu.dcache.total_refs 1134 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use +system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.437500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.437500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6886000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency -system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6886000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses -system.cpu.icache.demand_misses 256 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4621 # number of overall hits -system.cpu.icache.overall_miss_latency 6886000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses -system.cpu.icache.overall_misses 256 # number of overall misses +system.cpu.icache.overall_hits 5127 # number of overall hits +system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6118000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -136,10 +136,10 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.043041 # Cycle average of tags in use -system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use +system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -152,16 +152,16 @@ system.cpu.l2cache.ReadExReq_misses 81 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7061000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -173,38 +173,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992327 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 388 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4268000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992327 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 388 # number of overall misses +system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4268000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -217,16 +217,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.841445 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 33324 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 34630 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 4d51e2838..9fab97574 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:08 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:56 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 16662000 because target called exit() +Hello World!Exiting @ tick 17315000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 569d4b220..40d1ca238 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index 5fd208e3f..ef5ccc7e6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 13744 # Simulator instruction rate (inst/s) -host_mem_usage 186320 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -host_tick_rate 7996070 # Simulator tick rate (ticks/s) +host_inst_rate 69477 # Simulator instruction rate (inst/s) +host_mem_usage 201612 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 40336760 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 8475 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4932000 # Number of ticks simulated +sim_insts 9511 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5529000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9865 # number of cpu cycles simulated -system.cpu.num_insts 8475 # Number of instructions executed -system.cpu.num_refs 1765 # Number of memory references +system.cpu.numCycles 11059 # number of cpu cycles simulated +system.cpu.num_insts 9511 # Number of instructions executed +system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index 99e187690..ada9a56fb 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:50:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:14:28 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 4932000 because target called exit() +Exiting @ tick 5529000 because target called exit() |