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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
commitc3d41a2def15cdaf2ac3984315f452dacc6a0884 (patch)
tree5324ebec3add54b934a841eee901983ac3463a7f /tests/quick/00.hello/ref
parentda2a4acc26ba264c3c4a12495776fd6a1c4fb133 (diff)
parent4acca8a0536d4445ed25b67edf571ae460446ab9 (diff)
downloadgem5-c3d41a2def15cdaf2ac3984315f452dacc6a0884.tar.xz
Merge with the main repo.
--HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'tests/quick/00.hello/ref')
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini10
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/inorder-timing/simout6
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini8
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/o3-timing/simout4
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-atomic/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini72
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats59
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini72
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats35
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini72
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats27
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini21
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats24
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini87
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats47
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini9
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/o3-timing/simout4
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini72
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats55
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini72
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats27
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini72
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats35
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini21
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats20
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini87
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats47
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt89
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini9
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/simout16
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt436
-rw-r--r--tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini9
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt466
-rw-r--r--tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini8
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/inorder-timing/simout4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini8
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/o3-timing/simout4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-atomic/simout4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini21
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini8
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing/simout4
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/power/linux/o3-timing/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/power/linux/o3-timing/simout6
-rw-r--r--tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/power/linux/simple-atomic/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/power/linux/simple-atomic/simout16
-rw-r--r--tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt69
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini10
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/inorder-timing/simout6
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-atomic/simout16
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini138
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats71
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout16
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini9
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing/simout16
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini10
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini22
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats32
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout8
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt19
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini10
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt18
133 files changed, 2374 insertions, 1834 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 56fbbd75c..b17544f09 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
index d51796d4d..ba10334c5 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 15:20:58
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 118e4e630..4ce82e64f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
sim_ticks 21216000 # Number of ticks simulated
+final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 29106 # Simulator instruction rate (inst/s)
-host_tick_rate 96412699 # Simulator tick rate (ticks/s)
-host_mem_usage 242900 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
+host_inst_rate 36015 # Simulator instruction rate (inst/s)
+host_tick_rate 119302866 # Simulator tick rate (ticks/s)
+host_mem_usage 207132 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 30016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 469 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 1414781297 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 907993967 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 1414781297 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index d63a5e401..db5baf5c5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index 7a521752f..6e993ab1c 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 15:52:45
-gem5 started Aug 20 2011 15:52:55
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 1aa86fca4..3b3d572bb 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 12004500 # Number of ticks simulated
+final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61962 # Simulator instruction rate (inst/s)
-host_tick_rate 116453376 # Simulator tick rate (ticks/s)
-host_mem_usage 204272 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 38695 # Simulator instruction rate (inst/s)
+host_tick_rate 72731813 # Simulator tick rate (ticks/s)
+host_mem_usage 208040 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 6386 # Number of instructions simulated
+system.physmem.bytes_read 31040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 485 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2585697030 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1658044900 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2585697030 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 14af20ce8..df86e7077 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index c3032cdcb..9f50fe960 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:18:08
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index adb951856..7ceb6a8be 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 3215000 # Number of ticks simulated
+final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 887593 # Simulator instruction rate (inst/s)
-host_tick_rate 444402423 # Simulator tick rate (ticks/s)
-host_mem_usage 183180 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 76916 # Simulator instruction rate (inst/s)
+host_tick_rate 38606134 # Simulator tick rate (ticks/s)
+host_mem_usage 198176 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 34460 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 6696 # Number of bytes written to this memory
+system.physmem.num_reads 7599 # Number of read requests responded to by this memory
+system.physmem.num_writes 865 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10718506998 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7980093313 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2082737170 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12801244168 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index cd6b55738..b9fd9c5f2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
to_mem_ctrl_latency=1
transitions_per_cycle=32
version=0
@@ -119,7 +123,7 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
@@ -129,7 +133,8 @@ l1_response_latency=2
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
to_l2_latency=1
transitions_per_cycle=32
version=0
@@ -137,6 +142,7 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
@@ -145,11 +151,27 @@ start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
@@ -160,6 +182,7 @@ l2_request_latency=2
l2_response_latency=2
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
to_l1_latency=1
transitions_per_cycle=32
version=0
@@ -167,6 +190,7 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
@@ -180,35 +204,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -218,6 +225,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -304,8 +312,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 658d83110..c2d3c97af 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 14:32:56
+Real time: Jan/23/2012 04:21:55
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
-Virtual_time_in_seconds: 0.59
-Virtual_time_in_minutes: 0.00983333
-Virtual_time_in_hours: 0.000163889
-Virtual_time_in_days: 6.8287e-06
+Virtual_time_in_seconds: 0.38
+Virtual_time_in_minutes: 0.00633333
+Virtual_time_in_hours: 0.000105556
+Virtual_time_in_days: 4.39815e-06
Ruby_current_time: 279353
Ruby_start_time: 0
Ruby_cycles: 279353
-mbytes_resident: 39.4609
-mbytes_total: 222.137
-resident_ratio: 0.177678
+mbytes_resident: 45.5547
+mbytes_total: 214.371
+resident_ratio: 0.212504
ruby_cycles_executed: [ 279354 ]
@@ -119,11 +119,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11320
-page_faults: 0
+page_reclaims: 11862
+page_faults: 127
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 22816
+block_outputs: 96
Network Stats
-------------
@@ -198,20 +198,27 @@ links_utilized_percent_switch_3: 2.42686
outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory
- system.l1_cntrl0.L1IcacheMemory_total_misses: 0
- system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1IcacheMemory_total_misses: 691
+ system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 691
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
+
+ system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 691 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory
- system.l1_cntrl0.L1DcacheMemory_total_misses: 0
- system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1DcacheMemory_total_misses: 799
+ system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 799
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_request_type_LD: 72.9662%
+ system.l1_cntrl0.L1DcacheMemory_request_type_ST: 27.0338%
+
+ system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 799 100%
--- L1Cache ---
- Event Counts -
@@ -326,12 +333,17 @@ SINK_WB_ACK L1_Replacement [0 ] 0
SINK_WB_ACK WB_Ack [0 ] 0
Cache Stats: system.l2_cntrl0.L2cacheMemory
- system.l2_cntrl0.L2cacheMemory_total_misses: 0
- system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_misses: 1460
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1460
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_request_type_GETS: 39.0411%
+ system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 46.9863%
+ system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.9726%
+
+ system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1460 100%
--- L2Cache ---
- Event Counts -
@@ -625,4 +637,5 @@ M_DWRI Fetch [0 ] 0
M_DWRI Data [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DWRI DMA_READ [0 ] 0
-M_DWRI DMA_WRITE \ No newline at end of file
+M_DWRI DMA_WRITE [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 2f32125b9..c93c8f8af 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:32:19
-M5 started Apr 28 2011 14:32:56
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 23 2012 03:44:57
+gem5 started Jan 23 2012 04:21:53
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index d48699882..3bba58631 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 23386 # Simulator instruction rate (inst/s)
-host_mem_usage 227472 # Number of bytes of host memory used
-host_seconds 0.27 # Real time elapsed on the host
-host_tick_rate 1019507 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000279 # Number of seconds simulated
sim_ticks 279353 # Number of ticks simulated
-system.cpu.dtb.data_accesses 2060 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 2050 # DTB hits
-system.cpu.dtb.data_misses 10 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 2836 # Simulator instruction rate (inst/s)
+host_tick_rate 123728 # Simulator tick rate (ticks/s)
+host_mem_usage 219520 # Number of bytes of host memory used
+host_seconds 2.26 # Real time elapsed on the host
+sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 34460 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 6696 # Number of bytes written to this memory
+system.physmem.num_reads 7599 # Number of read requests responded to by this memory
+system.physmem.num_writes 865 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 123356470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 91840789 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 23969673 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 147326143 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 6432 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 279353 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 279353 # Number of busy cycles
-system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
-system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
-system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
-system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 279353 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index e475f8582..607ab419c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -118,7 +122,7 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
@@ -127,13 +131,15 @@ l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
@@ -142,11 +148,27 @@ start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
@@ -157,12 +179,14 @@ number_of_TBEs=256
recycle_latency=10
request_latency=2
response_latency=2
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
@@ -176,35 +200,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -214,6 +221,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -300,8 +308,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 0bc0d81dd..03b0eda65 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 14:49:15
+Real time: Jan/23/2012 04:22:13
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.61
-Virtual_time_in_minutes: 0.0101667
-Virtual_time_in_hours: 0.000169444
-Virtual_time_in_days: 7.06019e-06
+Virtual_time_in_seconds: 0.39
+Virtual_time_in_minutes: 0.0065
+Virtual_time_in_hours: 0.000108333
+Virtual_time_in_days: 4.51389e-06
Ruby_current_time: 223694
Ruby_start_time: 0
Ruby_cycles: 223694
-mbytes_resident: 39.6055
-mbytes_total: 222.41
-resident_ratio: 0.178127
+mbytes_resident: 45.5586
+mbytes_total: 214.484
+resident_ratio: 0.21241
ruby_cycles_executed: [ 223695 ]
@@ -119,11 +119,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11338
-page_faults: 0
+page_reclaims: 11886
+page_faults: 121
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 21600
+block_outputs: 88
Network Stats
-------------
@@ -1466,4 +1466,5 @@ MD PUTO [0 ] 0
MD PUTO_SHARERS [0 ] 0
MD DMA_READ [0 ] 0
MD DMA_WRITE [0 ] 0
-MD DMA_ACK \ No newline at end of file
+MD DMA_ACK [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index 79291085b..ed47704f6 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:48:31
-M5 started Apr 28 2011 14:49:14
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Jan 23 2012 03:47:36
+gem5 started Jan 23 2012 04:22:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 63f11d46d..44a6426b2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 19980 # Simulator instruction rate (inst/s)
-host_mem_usage 227752 # Number of bytes of host memory used
-host_seconds 0.32 # Real time elapsed on the host
-host_tick_rate 697544 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000224 # Number of seconds simulated
sim_ticks 223694 # Number of ticks simulated
-system.cpu.dtb.data_accesses 2060 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 2050 # DTB hits
-system.cpu.dtb.data_misses 10 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 19611 # Simulator instruction rate (inst/s)
+host_tick_rate 684980 # Simulator tick rate (ticks/s)
+host_mem_usage 219636 # Number of bytes of host memory used
+host_seconds 0.33 # Real time elapsed on the host
+sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 34460 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 6696 # Number of bytes written to this memory
+system.physmem.num_reads 7599 # Number of read requests responded to by this memory
+system.physmem.num_writes 865 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 154049729 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 114692392 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 29933749 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 183983477 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 6432 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 223694 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 223694 # Number of busy cycles
-system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
-system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
-system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
-system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 223694 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 9d759f6bf..e664ed4cf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -87,6 +90,7 @@ l2_select_num_bits=0
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -121,7 +125,7 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
@@ -136,13 +140,15 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
@@ -151,11 +157,27 @@ start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
@@ -168,12 +190,14 @@ l2_request_latency=5
l2_response_latency=5
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
size=512
@@ -187,35 +211,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -225,6 +232,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -311,8 +319,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index c3749a713..216172e7b 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 15:03:53
+Real time: Jan/23/2012 04:22:26
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.55
-Virtual_time_in_minutes: 0.00916667
-Virtual_time_in_hours: 0.000152778
-Virtual_time_in_days: 6.36574e-06
+Virtual_time_in_seconds: 0.31
+Virtual_time_in_minutes: 0.00516667
+Virtual_time_in_hours: 8.61111e-05
+Virtual_time_in_days: 3.58796e-06
Ruby_current_time: 231701
Ruby_start_time: 0
Ruby_cycles: 231701
-mbytes_resident: 39.457
-mbytes_total: 222.211
-resident_ratio: 0.177618
+mbytes_resident: 44.0234
+mbytes_total: 212.691
+resident_ratio: 0.206983
ruby_cycles_executed: [ 231702 ]
@@ -127,11 +127,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11316
-page_faults: 0
+page_reclaims: 11434
+page_faults: 122
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 21928
+block_outputs: 104
Network Stats
-------------
@@ -1039,4 +1039,5 @@ DR_L Tokens [0 ] 0
DR_L Request_Timeout [0 ] 0
DR_L DMA_READ [0 ] 0
DR_L DMA_WRITE [0 ] 0
-DR_L DMA_WRITE_All_Tokens \ No newline at end of file
+DR_L DMA_WRITE_All_Tokens [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index 8c53e7b8f..6ef144b06 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 15:03:17
-M5 started Apr 28 2011 15:03:52
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Jan 23 2012 03:50:16
+gem5 started Jan 23 2012 04:22:25
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index a5ec386b7..4911f0b0e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 32190 # Simulator instruction rate (inst/s)
-host_mem_usage 227548 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
-host_tick_rate 1163713 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000232 # Number of seconds simulated
sim_ticks 231701 # Number of ticks simulated
-system.cpu.dtb.data_accesses 2060 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 2050 # DTB hits
-system.cpu.dtb.data_misses 10 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 23819 # Simulator instruction rate (inst/s)
+host_tick_rate 861729 # Simulator tick rate (ticks/s)
+host_mem_usage 217800 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
+sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 34460 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 6696 # Number of bytes written to this memory
+system.physmem.num_reads 7599 # Number of read requests responded to by this memory
+system.physmem.num_writes 865 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 148726160 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 110728914 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 28899314 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 177625474 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 6432 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 231701 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 231701 # Number of busy cycles
-system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
-system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
-system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
-system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 231701 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 3c544cad1..aa987ffa6 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
memories=system.physmem
num_work_ids=16
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -65,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -200,11 +201,11 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
@@ -288,8 +289,14 @@ hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index c8eb7f5d6..15beb0d93 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/10/2012 12:41:50
+Real time: Jan/23/2012 04:21:44
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.28
-Virtual_time_in_minutes: 0.00466667
-Virtual_time_in_hours: 7.77778e-05
-Virtual_time_in_days: 3.24074e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours: 8.33333e-05
+Virtual_time_in_days: 3.47222e-06
Ruby_current_time: 208400
Ruby_start_time: 0
Ruby_cycles: 208400
-mbytes_resident: 39.0547
-mbytes_total: 234.742
-resident_ratio: 0.166439
+mbytes_resident: 43.3594
+mbytes_total: 212.09
+resident_ratio: 0.204439
ruby_cycles_executed: [ 208401 ]
@@ -126,11 +126,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10898
-page_faults: 53
+page_reclaims: 11268
+page_faults: 126
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 22864
+block_outputs: 104
Network Stats
-------------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 88e64f8c5..fa89dfcd6 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 10 2012 12:41:45
-gem5 started Jan 10 2012 12:41:49
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled Jan 23 2012 03:42:19
+gem5 started Jan 23 2012 04:21:43
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 76c45d699..dfbcac63c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000208 # Number of seconds simulated
sim_ticks 208400 # Number of ticks simulated
+final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 9071 # Simulator instruction rate (inst/s)
-host_tick_rate 295192 # Simulator tick rate (ticks/s)
-host_mem_usage 240380 # Number of bytes of host memory used
-host_seconds 0.71 # Real time elapsed on the host
+host_inst_rate 24253 # Simulator instruction rate (inst/s)
+host_tick_rate 789193 # Simulator tick rate (ticks/s)
+host_mem_usage 217184 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 34460 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 6696 # Number of bytes written to this memory
+system.physmem.num_reads 7599 # Number of read requests responded to by this memory
+system.physmem.num_writes 865 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 165355086 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 123109405 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 32130518 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 197485605 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 3c80d1144..0772d2ee5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -118,17 +122,43 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
+children=cacheMemory sequencer
buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.physmem]
type=PhysicalMemory
file=
@@ -137,44 +167,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
@@ -184,6 +188,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -248,8 +253,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index a8866f347..c9b06e2ad 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 14:27:56
+Real time: Jan/23/2012 04:58:59
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.44
-Virtual_time_in_minutes: 0.00733333
-Virtual_time_in_hours: 0.000122222
-Virtual_time_in_days: 5.09259e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours: 8.33333e-05
+Virtual_time_in_days: 3.47222e-06
Ruby_current_time: 342698
Ruby_start_time: 0
Ruby_cycles: 342698
-mbytes_resident: 38.9805
-mbytes_total: 221.645
-resident_ratio: 0.175922
+mbytes_resident: 44.5703
+mbytes_total: 213.352
+resident_ratio: 0.208905
ruby_cycles_executed: [ 342699 ]
@@ -122,11 +122,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11208
-page_faults: 3
+page_reclaims: 11770
+page_faults: 1
swaps: 0
-block_inputs: 1184
-block_outputs: 0
+block_inputs: 8
+block_outputs: 88
Network Stats
-------------
@@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 2.52117
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
- system.ruby.cpu_ruby_ports.dcache_total_misses: 1730
- system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1730
- system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+ system.l1_cntrl0.cacheMemory_total_misses: 1730
+ system.l1_cntrl0.cacheMemory_total_demand_misses: 1730
+ system.l1_cntrl0.cacheMemory_total_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_request_type_LD: 42.0231%
- system.ruby.cpu_ruby_ports.dcache_request_type_ST: 15.7803%
- system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 42.1965%
+ system.l1_cntrl0.cacheMemory_request_type_LD: 42.0231%
+ system.l1_cntrl0.cacheMemory_request_type_ST: 15.7803%
+ system.l1_cntrl0.cacheMemory_request_type_IFETCH: 42.1965%
- system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 1730 100%
+ system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1730 100%
--- L1Cache ---
- Event Counts -
@@ -307,4 +307,5 @@ ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
-ID_W Memory_Ack \ No newline at end of file
+ID_W Memory_Ack [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 50fcbd6d8..9cf822901 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:26:41
-M5 started Apr 28 2011 14:27:56
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index d3a7d6e19..beb747c41 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 36559 # Simulator instruction rate (inst/s)
-host_mem_usage 226968 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
-host_tick_rate 1954466 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000343 # Number of seconds simulated
sim_ticks 342698 # Number of ticks simulated
-system.cpu.dtb.data_accesses 2060 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 2050 # DTB hits
-system.cpu.dtb.data_misses 10 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 32385 # Simulator instruction rate (inst/s)
+host_tick_rate 1732860 # Simulator tick rate (ticks/s)
+host_mem_usage 218476 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
+sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 34460 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 6696 # Number of bytes written to this memory
+system.physmem.num_reads 7599 # Number of read requests responded to by this memory
+system.physmem.num_writes 865 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 100555008 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 74864750 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 19539069 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 120094077 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 6432 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 342698 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 342698 # Number of busy cycles
-system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
-system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
-system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
-system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 342698 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 49928ea02..f51983ecf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index ae153f79d..d977e688b 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:43:56
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 73820fcfc..84a161e81 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000033 # Number of seconds simulated
sim_ticks 33007000 # Number of ticks simulated
+final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 622879 # Simulator instruction rate (inst/s)
-host_tick_rate 3204159632 # Simulator tick rate (ticks/s)
-host_mem_usage 191816 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 110064 # Simulator instruction rate (inst/s)
+host_tick_rate 566999999 # Simulator tick rate (ticks/s)
+host_mem_usage 206896 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+system.physmem.bytes_read 28544 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 446 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index c7e464eb4..f0e8b9ebf 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index f41676f5c..2afd9a6f8 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 15:52:45
-gem5 started Aug 20 2011 15:52:55
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index d7cfe3b16..d94c5613d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000007 # Number of seconds simulated
sim_ticks 6833000 # Number of ticks simulated
+final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 39761 # Simulator instruction rate (inst/s)
-host_tick_rate 113766137 # Simulator tick rate (ticks/s)
-host_mem_usage 203344 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 46364 # Simulator instruction rate (inst/s)
+host_tick_rate 132671945 # Simulator tick rate (ticks/s)
+host_mem_usage 207164 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
+system.physmem.bytes_read 17280 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 270 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 43e841230..fad1e21b6 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 534040190..fdc12b275 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:00:19
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 50ec4667d..23e50fd7f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 343171 # Simulator instruction rate (inst/s)
-host_mem_usage 194176 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 169102503 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 1297500 # Number of ticks simulated
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 182014 # Simulator instruction rate (inst/s)
+host_tick_rate 91451888 # Simulator tick rate (ticks/s)
+host_mem_usage 197324 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+sim_insts 2577 # Number of instructions simulated
+system.physmem.bytes_read 13356 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2058 # Number of bytes written to this memory
+system.physmem.num_reads 3000 # Number of read requests responded to by this memory
+system.physmem.num_writes 294 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10293641618 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7969171484 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1586127168 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11879768786 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 2596 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2585 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 2596 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 2596 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 2596 # Number of busy cycles
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
-system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 2596 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index 255bc7bf6..89c8aeac1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
to_mem_ctrl_latency=1
transitions_per_cycle=32
version=0
@@ -119,7 +123,7 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
@@ -129,7 +133,8 @@ l1_response_latency=2
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
to_l2_latency=1
transitions_per_cycle=32
version=0
@@ -137,6 +142,7 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
@@ -145,11 +151,27 @@ start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
@@ -160,6 +182,7 @@ l2_request_latency=2
l2_response_latency=2
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
to_l1_latency=1
transitions_per_cycle=32
version=0
@@ -167,6 +190,7 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
@@ -180,35 +204,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -218,6 +225,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -304,8 +312,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 475d0c631..1c4da6ce4 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 14:32:56
+Real time: Jan/23/2012 04:21:58
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
-Virtual_time_in_seconds: 0.44
-Virtual_time_in_minutes: 0.00733333
-Virtual_time_in_hours: 0.000122222
-Virtual_time_in_days: 5.09259e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours: 7.22222e-05
+Virtual_time_in_days: 3.00926e-06
Ruby_current_time: 104867
Ruby_start_time: 0
Ruby_cycles: 104867
-mbytes_resident: 38.1289
-mbytes_total: 221.148
-resident_ratio: 0.172449
+mbytes_resident: 43.0078
+mbytes_total: 212.113
+resident_ratio: 0.202759
ruby_cycles_executed: [ 104868 ]
@@ -119,11 +119,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10981
+page_reclaims: 11317
page_faults: 0
swaps: 0
block_inputs: 0
-block_outputs: 0
+block_outputs: 88
Network Stats
-------------
@@ -198,20 +198,27 @@ links_utilized_percent_switch_3: 2.43896
outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory
- system.l1_cntrl0.L1IcacheMemory_total_misses: 0
- system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1IcacheMemory_total_misses: 300
+ system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 300
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
+
+ system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 300 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory
- system.l1_cntrl0.L1DcacheMemory_total_misses: 0
- system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1DcacheMemory_total_misses: 272
+ system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 272
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75%
+ system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25%
+
+ system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 272 100%
--- L1Cache ---
- Event Counts -
@@ -326,12 +333,17 @@ SINK_WB_ACK L1_Replacement [0 ] 0
SINK_WB_ACK WB_Ack [0 ] 0
Cache Stats: system.l2_cntrl0.L2cacheMemory
- system.l2_cntrl0.L2cacheMemory_total_misses: 0
- system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_misses: 547
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 547
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_request_type_GETS: 35.1005%
+ system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 53.1993%
+ system.l2_cntrl0.L2cacheMemory_request_type_GETX: 11.7002%
+
+ system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 547 100%
--- L2Cache ---
- Event Counts -
@@ -625,4 +637,5 @@ M_DWRI Fetch [0 ] 0
M_DWRI Data [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DWRI DMA_READ [0 ] 0
-M_DWRI DMA_WRITE \ No newline at end of file
+M_DWRI DMA_WRITE [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index 6b701bc22..dc0ba2922 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:32:19
-M5 started Apr 28 2011 14:32:56
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 23 2012 03:44:57
+gem5 started Jan 23 2012 04:21:56
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 78fb6974d..ebac3fa83 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 23624 # Simulator instruction rate (inst/s)
-host_mem_usage 226460 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-host_tick_rate 959767 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000105 # Number of seconds simulated
sim_ticks 104867 # Number of ticks simulated
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 1196 # Simulator instruction rate (inst/s)
+host_tick_rate 48657 # Simulator tick rate (ticks/s)
+host_mem_usage 217208 # Number of bytes of host memory used
+host_seconds 2.16 # Real time elapsed on the host
+sim_insts 2577 # Number of instructions simulated
+system.physmem.bytes_read 13356 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2058 # Number of bytes written to this memory
+system.physmem.num_reads 3000 # Number of read requests responded to by this memory
+system.physmem.num_writes 294 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 127361324 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 98601085 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 19624858 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 146986182 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 2597 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 104867 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 104867 # Number of busy cycles
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
-system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 104867 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index bc15f031c..e5748fef4 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -118,7 +122,7 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
@@ -127,13 +131,15 @@ l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
@@ -142,11 +148,27 @@ start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
@@ -157,12 +179,14 @@ number_of_TBEs=256
recycle_latency=10
request_latency=2
response_latency=2
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
@@ -176,35 +200,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -214,6 +221,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -300,8 +308,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 2d6c597b0..f2273438f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 14:49:15
+Real time: Jan/23/2012 04:22:12
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours: 0.000119444
-Virtual_time_in_days: 4.97685e-06
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours: 6.94444e-05
+Virtual_time_in_days: 2.89352e-06
Ruby_current_time: 85418
Ruby_start_time: 0
Ruby_cycles: 85418
-mbytes_resident: 38.2812
-mbytes_total: 221.418
-resident_ratio: 0.172944
+mbytes_resident: 42.9688
+mbytes_total: 212.301
+resident_ratio: 0.202396
ruby_cycles_executed: [ 85419 ]
@@ -119,11 +119,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11009
-page_faults: 0
+page_reclaims: 11325
+page_faults: 11
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1584
+block_outputs: 88
Network Stats
-------------
@@ -1466,4 +1466,5 @@ MD PUTO [0 ] 0
MD PUTO_SHARERS [0 ] 0
MD DMA_READ [0 ] 0
MD DMA_WRITE [0 ] 0
-MD DMA_ACK \ No newline at end of file
+MD DMA_ACK [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 220322bcb..0529ad1d8 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:48:31
-M5 started Apr 28 2011 14:49:14
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Jan 23 2012 03:47:36
+gem5 started Jan 23 2012 04:22:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index ec1a43e55..8d97fa8c6 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 20652 # Simulator instruction rate (inst/s)
-host_mem_usage 226736 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
-host_tick_rate 683514 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000085 # Number of seconds simulated
sim_ticks 85418 # Number of ticks simulated
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 13096 # Simulator instruction rate (inst/s)
+host_tick_rate 434048 # Simulator tick rate (ticks/s)
+host_mem_usage 217400 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
+sim_insts 2577 # Number of instructions simulated
+system.physmem.bytes_read 13356 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2058 # Number of bytes written to this memory
+system.physmem.num_reads 3000 # Number of read requests responded to by this memory
+system.physmem.num_writes 294 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 156360486 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 121051769 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 24093282 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 180453769 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 2597 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 85418 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 85418 # Number of busy cycles
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
-system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 85418 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 9580d477f..4c0569af0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -87,6 +90,7 @@ l2_select_num_bits=0
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -121,7 +125,7 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
@@ -136,13 +140,15 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
@@ -151,11 +157,27 @@ start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
@@ -168,12 +190,14 @@ l2_request_latency=5
l2_response_latency=5
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
size=512
@@ -187,35 +211,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -225,6 +232,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -311,8 +319,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 5aab6882e..2d266c770 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 15:03:52
+Real time: Jan/23/2012 04:22:26
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours: 0.000119444
-Virtual_time_in_days: 4.97685e-06
+Virtual_time_in_seconds: 0.22
+Virtual_time_in_minutes: 0.00366667
+Virtual_time_in_hours: 6.11111e-05
+Virtual_time_in_days: 2.5463e-06
Ruby_current_time: 87899
Ruby_start_time: 0
Ruby_cycles: 87899
-mbytes_resident: 38.1484
-mbytes_total: 221.172
-resident_ratio: 0.172536
+mbytes_resident: 42.2227
+mbytes_total: 211.34
+resident_ratio: 0.199786
ruby_cycles_executed: [ 87900 ]
@@ -127,11 +127,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10978
-page_faults: 0
+page_reclaims: 11088
+page_faults: 5
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1064
+block_outputs: 104
Network Stats
-------------
@@ -1032,4 +1032,5 @@ DR_L Tokens [0 ] 0
DR_L Request_Timeout [0 ] 0
DR_L DMA_READ [0 ] 0
DR_L DMA_WRITE [0 ] 0
-DR_L DMA_WRITE_All_Tokens \ No newline at end of file
+DR_L DMA_WRITE_All_Tokens [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 4114133be..476a0b599 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 15:03:17
-M5 started Apr 28 2011 15:03:52
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Jan 23 2012 03:50:16
+gem5 started Jan 23 2012 04:22:25
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 58dca509c..fd5600236 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 33219 # Simulator instruction rate (inst/s)
-host_mem_usage 226484 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 1130708 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87899 # Number of ticks simulated
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 12702 # Simulator instruction rate (inst/s)
+host_tick_rate 433208 # Simulator tick rate (ticks/s)
+host_mem_usage 216416 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
+sim_insts 2577 # Number of instructions simulated
+system.physmem.bytes_read 13356 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2058 # Number of bytes written to this memory
+system.physmem.num_reads 3000 # Number of read requests responded to by this memory
+system.physmem.num_writes 294 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 151947121 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 117635013 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 23413236 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 175360357 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 2597 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 87899 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 87899 # Number of busy cycles
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
-system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 87899 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index c04240cb3..209bb4d8d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
memories=system.physmem
num_work_ids=16
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -65,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -200,11 +201,11 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
@@ -288,8 +289,14 @@ hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index b81839414..452952d26 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/10/2012 12:42:00
+Real time: Jan/23/2012 04:21:49
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.21
-Virtual_time_in_minutes: 0.0035
-Virtual_time_in_hours: 5.83333e-05
-Virtual_time_in_days: 2.43056e-06
+Virtual_time_in_seconds: 0.23
+Virtual_time_in_minutes: 0.00383333
+Virtual_time_in_hours: 6.38889e-05
+Virtual_time_in_days: 2.66204e-06
Ruby_current_time: 78448
Ruby_start_time: 0
Ruby_cycles: 78448
-mbytes_resident: 37.832
-mbytes_total: 233.867
-resident_ratio: 0.161817
+mbytes_resident: 41.5938
+mbytes_total: 210.898
+resident_ratio: 0.197222
ruby_cycles_executed: [ 78449 ]
@@ -126,11 +126,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10644
+page_reclaims: 10974
page_faults: 0
swaps: 0
block_inputs: 0
-block_outputs: 0
+block_outputs: 88
Network Stats
-------------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 01a9c1b54..20c68eff3 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 10 2012 12:41:45
-gem5 started Jan 10 2012 12:42:00
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+gem5 compiled Jan 23 2012 03:42:19
+gem5 started Jan 23 2012 04:21:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 3836f9bae..5c579e1af 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000078 # Number of seconds simulated
sim_ticks 78448 # Number of ticks simulated
+final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 54765 # Simulator instruction rate (inst/s)
-host_tick_rate 1666412 # Simulator tick rate (ticks/s)
-host_mem_usage 239484 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 29294 # Simulator instruction rate (inst/s)
+host_tick_rate 891567 # Simulator tick rate (ticks/s)
+host_mem_usage 215964 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+system.physmem.bytes_read 13356 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2058 # Number of bytes written to this memory
+system.physmem.num_reads 3000 # Number of read requests responded to by this memory
+system.physmem.num_writes 294 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 170252906 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 131807057 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 26233938 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 196486845 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 2b74e07ae..2d5b16f7e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -118,17 +122,43 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
+children=cacheMemory sequencer
buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.physmem]
type=PhysicalMemory
file=
@@ -137,44 +167,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
@@ -184,6 +188,7 @@ buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
@@ -248,8 +253,16 @@ type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index 4b75a7bdf..2c26f3344 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/28/2011 14:27:10
+Real time: Jan/23/2012 04:59:27
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.34
-Virtual_time_in_minutes: 0.00566667
-Virtual_time_in_hours: 9.44444e-05
-Virtual_time_in_days: 3.93519e-06
+Virtual_time_in_seconds: 0.24
+Virtual_time_in_minutes: 0.004
+Virtual_time_in_hours: 6.66667e-05
+Virtual_time_in_days: 2.77778e-06
Ruby_current_time: 123378
Ruby_start_time: 0
Ruby_cycles: 123378
-mbytes_resident: 37.6602
-mbytes_total: 220.656
-resident_ratio: 0.170727
+mbytes_resident: 42.25
+mbytes_total: 211.328
+resident_ratio: 0.199926
ruby_cycles_executed: [ 123379 ]
@@ -122,11 +122,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10875
-page_faults: 4
+page_reclaims: 11154
+page_faults: 0
swaps: 0
-block_inputs: 2528
-block_outputs: 0
+block_inputs: 0
+block_outputs: 88
Network Stats
-------------
@@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 2.52881
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
- system.ruby.cpu_ruby_ports.dcache_total_misses: 626
- system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626
- system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+ system.l1_cntrl0.cacheMemory_total_misses: 626
+ system.l1_cntrl0.cacheMemory_total_demand_misses: 626
+ system.l1_cntrl0.cacheMemory_total_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_request_type_LD: 39.1374%
- system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.4185%
- system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 47.4441%
+ system.l1_cntrl0.cacheMemory_request_type_LD: 39.1374%
+ system.l1_cntrl0.cacheMemory_request_type_ST: 13.4185%
+ system.l1_cntrl0.cacheMemory_request_type_IFETCH: 47.4441%
- system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 626 100%
+ system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 626 100%
--- L1Cache ---
- Event Counts -
@@ -307,4 +307,5 @@ ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
-ID_W Memory_Ack \ No newline at end of file
+ID_W Memory_Ack [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 43151ea3c..af1c56980 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:26:41
-M5 started Apr 28 2011 14:27:10
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 9c0c161ed..bcff12bb9 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 38181 # Simulator instruction rate (inst/s)
-host_mem_usage 225956 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 1823203 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000123 # Number of seconds simulated
sim_ticks 123378 # Number of ticks simulated
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 44691 # Simulator instruction rate (inst/s)
+host_tick_rate 2138947 # Simulator tick rate (ticks/s)
+host_mem_usage 216404 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+sim_insts 2577 # Number of instructions simulated
+system.physmem.bytes_read 13356 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2058 # Number of bytes written to this memory
+system.physmem.num_reads 3000 # Number of read requests responded to by this memory
+system.physmem.num_writes 294 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 108252687 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 83807486 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 16680445 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 124933132 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 2597 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 123378 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 123378 # Number of busy cycles
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
-system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 123378 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 965487eb2..72df69882 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 363499d94..6a994fb76 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 11:58:24
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index a8a5eaa16..e3a7a00a0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,249 +1,259 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 195987 # Simulator instruction rate (inst/s)
-host_mem_usage 201848 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 1258278911 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
sim_ticks 16769000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 627 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 82 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
-system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 297044 # Simulator instruction rate (inst/s)
+host_tick_rate 1928782837 # Simulator tick rate (ticks/s)
+host_mem_usage 206044 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+sim_insts 2577 # Number of instructions simulated
+system.physmem.bytes_read 15680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 245 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 935058739 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 622100304 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 935058739 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.numCycles 33538 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_store_insts 298 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 33538 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use
+system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
+system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 2423 # number of overall hits
+system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
+system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 163 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
-system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 2423 # number of overall hits
-system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
-system.cpu.icache.overall_misses 163 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use
-system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 2597 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 2586 # ITB hits
-system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
+system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
+system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 627 # number of overall hits
+system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
+system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 82 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy
+system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 0 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 245 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 245 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 33538 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 33538 # Number of busy cycles
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
-system.cpu.num_int_insts 2375 # number of integer instructions
-system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_load_insts 419 # Number of load instructions
-system.cpu.num_mem_refs 717 # number of memory refs
-system.cpu.num_store_insts 298 # Number of store instructions
-system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index 35f7f2ba7..21dc694d7 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 2cb4f1a9c..f402d7e9e 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 19:01:51
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index 3aaa40ec4..19b87b225 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
sim_ticks 10001500 # Number of ticks simulated
+final_tick 10001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48143 # Simulator instruction rate (inst/s)
-host_tick_rate 83889434 # Simulator tick rate (ticks/s)
-host_mem_usage 212568 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 15723 # Simulator instruction rate (inst/s)
+host_tick_rate 27400304 # Simulator tick rate (ticks/s)
+host_mem_usage 218472 # Number of bytes of host memory used
+host_seconds 0.37 # Real time elapsed on the host
sim_insts 5739 # Number of instructions simulated
+system.physmem.bytes_read 25856 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 404 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2585212218 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1785332200 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2585212218 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
index 327106c53..1ee45ad85 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
index 974d1c8f4..13e73ddc3 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:32:52
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 1364619fb..8e7751fe7 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 931505 # Simulator instruction rate (inst/s)
-host_mem_usage 249344 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 451909477 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5739 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2875500 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 25921 # Simulator instruction rate (inst/s)
+host_tick_rate 12986430 # Simulator tick rate (ticks/s)
+host_mem_usage 208728 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
+sim_insts 5739 # Number of instructions simulated
+system.physmem.bytes_read 22944 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3648 # Number of bytes written to this memory
+system.physmem.num_reads 5771 # Number of read requests responded to by this memory
+system.physmem.num_writes 924 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 5752 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 5752 # Number of busy cycles
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 5739 # Number of instructions executed
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 185 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
-system.cpu.num_load_insts 1201 # Number of load instructions
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 2139 # number of memory refs
+system.cpu.num_load_insts 1201 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
-system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5752 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
index 4214b8570..d881a3977 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
index e4f30d324..25474862b 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:33:02
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
index e792babc2..9108e20ee 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,264 +1,274 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 534023 # Simulator instruction rate (inst/s)
-host_mem_usage 257088 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2428466145 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5682 # Number of instructions simulated
sim_seconds 0.000026 # Number of seconds simulated
sim_ticks 26361000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 870 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7224000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.068447 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 141 # number of demand (read+write) misses
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-system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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+system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency
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+system.cpu.itb.accesses 0 # DTB accesses
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+system.cpu.num_fp_insts 16 # number of float instructions
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+system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
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+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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+system.cpu.num_busy_cycles 52722 # Number of busy cycles
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system.cpu.icache.ReadReq_hits 4373 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.052232 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
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-system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.052232 # mshr miss rate for demand accesses
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-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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-system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses
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-system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use
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-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
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-system.cpu.itb.read_accesses 0 # DTB read accesses
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-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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+system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency
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+system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 32 # number of ReadReq hits
+system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 32 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 350 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.905605 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.916230 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 32 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 350 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 52722 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 52722 # Number of busy cycles
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 5682 # Number of instructions executed
-system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
-system.cpu.num_int_insts 4985 # number of integer instructions
-system.cpu.num_int_register_reads 28701 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
-system.cpu.num_load_insts 1201 # Number of load instructions
-system.cpu.num_mem_refs 2139 # number of memory refs
-system.cpu.num_store_insts 938 # Number of store instructions
-system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
index f9f4647e1..1ccb30b9c 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
index 86af758df..677598e87 100755
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:29
gem5 executing on zizzer
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 844338a8e..78172e7b6 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 19785000 # Number of ticks simulated
+final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1139 # Simulator instruction rate (inst/s)
-host_tick_rate 3867528 # Simulator tick rate (ticks/s)
-host_mem_usage 204696 # Number of bytes of host memory used
-host_seconds 5.12 # Real time elapsed on the host
+host_inst_rate 71616 # Simulator instruction rate (inst/s)
+host_tick_rate 243111037 # Simulator tick rate (ticks/s)
+host_mem_usage 208328 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+system.physmem.bytes_read 29120 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 455 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 1471822087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1025423300 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 1471822087 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
index 6a2ff3124..508c3cad4 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
index 1b7f6128f..eb1e6f70f 100755
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:41
gem5 executing on zizzer
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index 3721e6673..e49d82dd9 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 12272500 # Number of ticks simulated
+final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1003 # Simulator instruction rate (inst/s)
-host_tick_rate 2382032 # Simulator tick rate (ticks/s)
-host_mem_usage 205244 # Number of bytes of host memory used
-host_seconds 5.15 # Real time elapsed on the host
+host_inst_rate 65845 # Simulator instruction rate (inst/s)
+host_tick_rate 156294886 # Simulator tick rate (ticks/s)
+host_mem_usage 208908 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5169 # Number of instructions simulated
+system.physmem.bytes_read 30400 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 475 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2477082909 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1736565492 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2477082909 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index fda15903b..8bad8df13 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=MipsTLB
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 9eba211ea..4b9270f18 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:47
gem5 executing on zizzer
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 6bf960444..397c3f1f6 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2913500 # Number of ticks simulated
+final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1129 # Simulator instruction rate (inst/s)
-host_tick_rate 564724 # Simulator tick rate (ticks/s)
-host_mem_usage 195504 # Number of bytes of host memory used
-host_seconds 5.16 # Real time elapsed on the host
+host_inst_rate 231601 # Simulator instruction rate (inst/s)
+host_tick_rate 115720913 # Simulator tick rate (ticks/s)
+host_mem_usage 199128 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+system.physmem.bytes_read 27687 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3658 # Number of bytes written to this memory
+system.physmem.num_reads 6992 # Number of read requests responded to by this memory
+system.physmem.num_writes 925 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9503003261 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 8001372919 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1255534580 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 10758537841 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 41938cc87..e5b4b16c8 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -7,9 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -136,6 +138,7 @@ version=0
[system.l1_cntrl0.cacheMemory]
type=RubyCache
assoc=2
+is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
@@ -164,11 +167,11 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
@@ -252,8 +255,14 @@ hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index b0d2d6b62..f6eaf03f7 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:56
gem5 executing on zizzer
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index fe1143095..65d0aed82 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000293 # Number of seconds simulated
sim_ticks 292960 # Number of ticks simulated
+final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 1124 # Simulator instruction rate (inst/s)
-host_tick_rate 56528 # Simulator tick rate (ticks/s)
-host_mem_usage 213468 # Number of bytes of host memory used
-host_seconds 5.18 # Real time elapsed on the host
+host_inst_rate 55801 # Simulator instruction rate (inst/s)
+host_tick_rate 2804966 # Simulator tick rate (ticks/s)
+host_mem_usage 220172 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+system.physmem.bytes_read 27687 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3658 # Number of bytes written to this memory
+system.physmem.num_reads 6992 # Number of read requests responded to by this memory
+system.physmem.num_writes 925 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 94507783 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 79574003 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 12486346 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 106994129 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 383b176d8..36444e22d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index 09aaf2152..7525d1ad5 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:52
gem5 executing on zizzer
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index 0e8242f31..566ce19a4 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000032 # Number of seconds simulated
sim_ticks 32088000 # Number of ticks simulated
+final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1128 # Simulator instruction rate (inst/s)
-host_tick_rate 6214306 # Simulator tick rate (ticks/s)
-host_mem_usage 204312 # Number of bytes of host memory used
-host_seconds 5.16 # Real time elapsed on the host
+host_inst_rate 263412 # Simulator instruction rate (inst/s)
+host_tick_rate 1449372115 # Simulator tick rate (ticks/s)
+host_mem_usage 207940 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+system.physmem.bytes_read 28096 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 439 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
index a3775a1dd..fb36c719f 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -103,6 +105,7 @@ smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
+store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -477,7 +480,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +503,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +522,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +532,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
index d1cb3e246..8cb241542 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 15 2011 17:49:29
-gem5 started Jul 15 2011 20:14:11
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 03:58:39
+gem5 started Jan 23 2012 04:24:00
+gem5 executing on zizzer
command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
index bac6ac3e3..5a2ad1a0a 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 10910500 # Number of ticks simulated
+final_tick 10910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 31106 # Simulator instruction rate (inst/s)
-host_tick_rate 58503850 # Simulator tick rate (ticks/s)
-host_mem_usage 241340 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 80565 # Simulator instruction rate (inst/s)
+host_tick_rate 151515044 # Simulator tick rate (ticks/s)
+host_mem_usage 205800 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5800 # Number of instructions simulated
+system.physmem.bytes_read 28608 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 447 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2622061317 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2017872691 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2622061317 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
index c4bee2b32..f4325cdae 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +48,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=PowerTLB
@@ -86,7 +89,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +99,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
index c3d9ac55b..e45cd058f 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,5 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 30329336. This will break if not /dev/zero.
-For more information see: http://www.m5sim.org/warn/3a2134f6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
index 86b3ce749..ef2f9ace6 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:26
-M5 started Apr 19 2011 12:19:32
-M5 executing on maize
-command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
+gem5 compiled Jan 23 2012 03:58:39
+gem5 started Jan 23 2012 04:24:03
+gem5 executing on zizzer
+command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
index c1d1657bb..5070ee2a1 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -1,52 +1,63 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 259061 # Simulator instruction rate (inst/s)
-host_mem_usage 193868 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 128464915 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5801 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2900000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
+final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 305071 # Simulator instruction rate (inst/s)
+host_tick_rate 152367478 # Simulator tick rate (ticks/s)
+host_mem_usage 196296 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 5801 # Number of instructions simulated
+system.physmem.bytes_read 26925 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 4209 # Number of bytes written to this memory
+system.physmem.num_reads 6763 # Number of read requests responded to by this memory
+system.physmem.num_writes 1046 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9284482759 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 8001379310 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1451379310 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 10735862069 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.numCycles 5801 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 5801 # Number of busy cycles
-system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses
-system.cpu.num_fp_insts 22 # number of float instructions
-system.cpu.num_fp_register_reads 20 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_func_calls 200 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 5801 # Number of instructions executed
system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses
+system.cpu.num_func_calls 200 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls
system.cpu.num_int_insts 5706 # number of integer instructions
+system.cpu.num_fp_insts 22 # number of float instructions
system.cpu.num_int_register_reads 9541 # number of times the integer registers were read
system.cpu.num_int_register_writes 5005 # number of times the integer registers were written
-system.cpu.num_load_insts 962 # Number of load instructions
+system.cpu.num_fp_register_reads 20 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2008 # number of memory refs
+system.cpu.num_load_insts 962 # Number of load instructions
system.cpu.num_store_insts 1046 # Number of store instructions
-system.cpu.workload.num_syscalls 9 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5801 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini
index f7a4ddc40..32a7f4ad9 100644
--- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/arm/scratch/sysexplr/dist/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout
index 002338518..024efc4d5 100755
--- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 9 2011 14:58:11
-gem5 started Jul 9 2011 15:02:19
-gem5 executing on nadc-0321
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:09
+gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 1b5682411..1ce5039d0 100644
--- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18201500 # Number of ticks simulated
+final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63270 # Simulator instruction rate (inst/s)
-host_tick_rate 215616708 # Simulator tick rate (ticks/s)
-host_mem_usage 249768 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 29731 # Simulator instruction rate (inst/s)
+host_tick_rate 101330259 # Simulator tick rate (ticks/s)
+host_mem_usage 213072 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+system.physmem.bytes_read 27072 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 423 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 36404 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index fe9f8a548..8aa4dc707 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=SparcTLB
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index a3abc632d..9cbff76e8 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:20:06
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:11
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 2701000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index fcb8d359c..57eaeacb0 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2701000 # Number of ticks simulated
+final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 639191 # Simulator instruction rate (inst/s)
-host_tick_rate 322368277 # Simulator tick rate (ticks/s)
-host_mem_usage 216400 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 117056 # Simulator instruction rate (inst/s)
+host_tick_rate 59184907 # Simulator tick rate (ticks/s)
+host_mem_usage 203964 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+system.physmem.bytes_read 26135 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5065 # Number of bytes written to this memory
+system.physmem.num_reads 6099 # Number of read requests responded to by this memory
+system.physmem.num_writes 673 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9676045909 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7971862273 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1875231396 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11551277305 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 5403 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index aacea45cb..e13b78d74 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=SparcTLB
@@ -78,11 +81,13 @@ uid=100
type=Directory_Controller
children=directory memBuffer
buffer_size=0
+cntrl_id=1
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -117,16 +122,43 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
+children=cacheMemory sequencer
buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
+cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.physmem]
type=PhysicalMemory
file=
@@ -135,44 +167,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
@@ -180,59 +186,83 @@ children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
-endpoint_bandwidth=10000
-link_latency=1
+endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-num_int_nodes=3
print_config=false
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.l1_cntrl0
-int_node=0
+int_node=system.ruby.network.topology.routers0
latency=1
+link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.dir_cntrl0
-int_node=1
+int_node=system.ruby.network.topology.routers1
latency=1
+link_id=1
weight=1
[system.ruby.network.topology.int_links0]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=0
-node_b=2
+link_id=2
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=1
-node_b=2
+link_id=3
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
weight=1
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index e4482bc0d..d48e9e1d8 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/19/2011 12:21:28
+Real time: Jan/23/2012 04:24:20
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.16
-Virtual_time_in_minutes: 0.00266667
-Virtual_time_in_hours: 4.44444e-05
-Virtual_time_in_days: 1.85185e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours: 7.22222e-05
+Virtual_time_in_days: 3.00926e-06
Ruby_current_time: 253364
Ruby_start_time: 0
Ruby_cycles: 253364
-mbytes_resident: 38.7109
-mbytes_total: 208.668
-resident_ratio: 0.185533
+mbytes_resident: 45.418
+mbytes_total: 219.465
+resident_ratio: 0.206949
ruby_cycles_executed: [ 253365 ]
@@ -122,11 +122,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10204
-page_faults: 0
+page_reclaims: 12012
+page_faults: 1
swaps: 0
-block_inputs: 0
-block_outputs: 64
+block_inputs: 152
+block_outputs: 88
Network Stats
-------------
@@ -139,9 +139,9 @@ total_msgs: 15444 total_bytes: 617760
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.158621
- links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 2.53982
+ links_utilized_percent_switch_0_link_0: 2.54298 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 2.53667 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
@@ -150,9 +150,9 @@ links_utilized_percent_switch_0: 0.158621
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.158857
- links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 2.53982
+ links_utilized_percent_switch_1_link_0: 2.53667 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 2.54298 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
@@ -161,27 +161,27 @@ links_utilized_percent_switch_1: 0.158857
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.253982
- links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 2.53982
+ links_utilized_percent_switch_2_link_0: 2.54298 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 2.53667 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
- system.ruby.cpu_ruby_ports.dcache_total_misses: 1289
- system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289
- system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+ system.l1_cntrl0.cacheMemory_total_misses: 1289
+ system.l1_cntrl0.cacheMemory_total_demand_misses: 1289
+ system.l1_cntrl0.cacheMemory_total_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_request_type_LD: 30.6439%
- system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.8867%
- system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 55.4694%
+ system.l1_cntrl0.cacheMemory_request_type_LD: 30.6439%
+ system.l1_cntrl0.cacheMemory_request_type_ST: 13.8867%
+ system.l1_cntrl0.cacheMemory_request_type_IFETCH: 55.4694%
- system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 1289 100%
+ system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1289 100%
--- L1Cache ---
- Event Counts -
@@ -227,9 +227,9 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_reads: 1289
memory_writes: 1285
memory_refreshes: 528
- memory_total_request_delays: 3552
- memory_delays_per_request: 1.37995
- memory_delays_in_input_queue: 1284
+ memory_total_request_delays: 2936
+ memory_delays_per_request: 1.14064
+ memory_delays_in_input_queue: 668
memory_delays_behind_head_of_bank_queue: 3
memory_delays_stalled_at_head_of_bank_queue: 2265
memory_stalls_for_bank_busy: 847
@@ -307,4 +307,5 @@ ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
-ID_W Memory_Ack \ No newline at end of file
+ID_W Memory_Ack [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index facf1db54..8b55b99bf 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:21:28
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:20
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 253364 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 44c0d650a..5fbe4680b 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000253 # Number of seconds simulated
sim_ticks 253364 # Number of ticks simulated
+final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 54602 # Simulator instruction rate (inst/s)
-host_tick_rate 2590295 # Simulator tick rate (ticks/s)
-host_mem_usage 234524 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 57666 # Simulator instruction rate (inst/s)
+host_tick_rate 2735530 # Simulator tick rate (ticks/s)
+host_mem_usage 224736 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+system.physmem.bytes_read 26135 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5065 # Number of bytes written to this memory
+system.physmem.num_reads 6099 # Number of read requests responded to by this memory
+system.physmem.num_writes 673 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 103151987 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 84984449 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 19991001 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 123142988 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 253364 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 87bc655de..31f964ca0 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 3cc40bf72..a3d57b80d 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:21:23
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:14
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 28206000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index a8d6eb9ee..0e1d1294b 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000028 # Number of seconds simulated
sim_ticks 28206000 # Number of ticks simulated
+final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 272526 # Simulator instruction rate (inst/s)
-host_tick_rate 1437682899 # Simulator tick rate (ticks/s)
-host_mem_usage 225224 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 103151 # Simulator instruction rate (inst/s)
+host_tick_rate 544654705 # Simulator tick rate (ticks/s)
+host_mem_usage 212680 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+system.physmem.bytes_read 24896 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 16320 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 389 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 882649082 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 578600298 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 882649082 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 56412 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
index 9ae1576ae..8582c91b4 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
index e8531dc26..4c371922e 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:37
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
index e3bb4b417..e2df7b059 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 11087000 # Number of ticks simulated
+final_tick 11087000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74834 # Simulator instruction rate (inst/s)
-host_tick_rate 84571612 # Simulator tick rate (ticks/s)
-host_mem_usage 239776 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 31087 # Simulator instruction rate (inst/s)
+host_tick_rate 35135175 # Simulator tick rate (ticks/s)
+host_mem_usage 212404 # Number of bytes of host memory used
+host_seconds 0.32 # Real time elapsed on the host
sim_insts 9809 # Number of instructions simulated
+system.physmem.bytes_read 28288 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 442 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2551456661 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1708667809 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2551456661 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 22175 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index b1b2b6764..e5a1ce348 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,7 +69,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 65af79972..de652c174 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:38
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 2f19e2e68..e2f539833 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 5651000 # Number of ticks simulated
+final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 855797 # Simulator instruction rate (inst/s)
-host_tick_rate 492033087 # Simulator tick rate (ticks/s)
-host_mem_usage 229652 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 225004 # Simulator instruction rate (inst/s)
+host_tick_rate 129531520 # Simulator tick rate (ticks/s)
+host_mem_usage 202604 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
sim_insts 9810 # Number of instructions simulated
+system.physmem.bytes_read 62348 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7110 # Number of bytes written to this memory
+system.physmem.num_reads 7966 # Number of read requests responded to by this memory
+system.physmem.num_writes 934 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11033091488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 9782339409 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1258184392 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12291275880 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 11303 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 752669beb..3ef5774b9 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -7,9 +7,10 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
mem_mode=timing
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -64,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -165,11 +167,11 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
[system.ruby]
type=RubySystem
-children=network profiler tracer
+children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
@@ -253,8 +255,14 @@ hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index b05082262..33342e3e3 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/09/2012 14:28:32
+Real time: Jan/23/2012 04:24:44
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.31
-Virtual_time_in_minutes: 0.00516667
-Virtual_time_in_hours: 8.61111e-05
-Virtual_time_in_days: 3.58796e-06
+Virtual_time_in_seconds: 0.27
+Virtual_time_in_minutes: 0.0045
+Virtual_time_in_hours: 7.5e-05
+Virtual_time_in_days: 3.125e-06
Ruby_current_time: 276484
Ruby_start_time: 0
Ruby_cycles: 276484
-mbytes_resident: 40.0625
-mbytes_total: 241.918
-resident_ratio: 0.165652
+mbytes_resident: 46.1367
+mbytes_total: 218.203
+resident_ratio: 0.211439
ruby_cycles_executed: [ 276485 ]
@@ -125,11 +125,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11175
-page_faults: 4
+page_reclaims: 12102
+page_faults: 2
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 144
+block_outputs: 88
Network Stats
-------------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 52f9aeb2f..9c1cf6357 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:43
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 58cff044f..49089d227 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000276 # Number of seconds simulated
sim_ticks 276484 # Number of ticks simulated
+final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 73084 # Simulator instruction rate (inst/s)
-host_tick_rate 2059440 # Simulator tick rate (ticks/s)
-host_mem_usage 247728 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 88128 # Simulator instruction rate (inst/s)
+host_tick_rate 2483404 # Simulator tick rate (ticks/s)
+host_mem_usage 223444 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 9810 # Number of instructions simulated
+system.physmem.bytes_read 62348 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7110 # Number of bytes written to this memory
+system.physmem.num_reads 7966 # Number of read requests responded to by this memory
+system.physmem.num_writes 934 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 225503103 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 199939237 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 25715774 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 251218877 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 276484 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index acea7ec29..36b722b34 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,7 +172,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index 045ceeef4..074c5468c 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:38
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index eb8aa1f61..dcf7af574 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000029 # Number of seconds simulated
sim_ticks 28768000 # Number of ticks simulated
+final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 524711 # Simulator instruction rate (inst/s)
-host_tick_rate 1537080573 # Simulator tick rate (ticks/s)
-host_mem_usage 238628 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 320748 # Simulator instruction rate (inst/s)
+host_tick_rate 940055576 # Simulator tick rate (ticks/s)
+host_mem_usage 211332 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 9810 # Number of instructions simulated
+system.physmem.bytes_read 23104 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 361 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 57536 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started