diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
| commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
| tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/quick/00.hello | |
| parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
| download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz | |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/quick/00.hello')
30 files changed, 832 insertions, 640 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1a19512dc..f58899eb3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 35d6ad747..ce1ae8d6f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 538 # Number of BTB hits -global.BPredUnit.BTBLookups 1681 # Number of BTB lookups +global.BPredUnit.BTBHits 562 # Number of BTB hits +global.BPredUnit.BTBLookups 1725 # Number of BTB lookups global.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 412 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1149 # Number of conditional branches predicted -global.BPredUnit.lookups 1984 # Number of BP lookups -global.BPredUnit.usedRAS 275 # Number of times the RAS was used to get a target. -host_inst_rate 62494 # Simulator instruction rate (inst/s) -host_mem_usage 196896 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 50069310 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 121 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1979 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1190 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.condIncorrect 409 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted +global.BPredUnit.lookups 2029 # Number of BP lookups +global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target. +host_inst_rate 9351 # Simulator instruction rate (inst/s) +host_mem_usage 180452 # Number of bytes of host memory used +host_seconds 0.60 # Real time elapsed on the host +host_tick_rate 7988790 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 124 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2030 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1236 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4515000 # Number of ticks simulated +sim_ticks 4806000 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 81 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 85 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 8177 +system.cpu.commit.COM:committed_per_cycle.samples 8660 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 5854 7159.10% - 1 1205 1473.65% - 2 403 492.85% - 3 188 229.91% - 4 133 162.65% - 5 98 119.85% - 6 110 134.52% - 7 105 128.41% - 8 81 99.06% + 0 6353 7336.03% + 1 1192 1376.44% + 2 402 464.20% + 3 185 213.63% + 4 132 152.42% + 5 93 107.39% + 6 110 127.02% + 7 108 124.71% + 8 85 98.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4015 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4234 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.584030 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.584030 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1416 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1055000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.065963 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 635000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065963 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 533 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26660.919540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5781.609195 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 446 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2319500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.163227 # miss rate for WriteReq accesses +system.cpu.cpi 1.680420 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.680420 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6357.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1437 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1023500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.063844 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 623000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.063844 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 27385.057471 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5839.080460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 442 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2382500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.164461 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 503000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.163227 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.164461 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.843931 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.141176 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2049 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18045.454545 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1862 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3374500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.091264 # miss rate for demand accesses -system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 311 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1138000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.091264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 187 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18410.810811 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1879 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3406000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.089632 # miss rate for demand accesses +system.cpu.dcache.demand_misses 185 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 314 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1131000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.089632 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2049 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18045.454545 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18410.810811 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1862 # number of overall hits -system.cpu.dcache.overall_miss_latency 3374500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.091264 # miss rate for overall accesses -system.cpu.dcache.overall_misses 187 # number of overall misses -system.cpu.dcache.overall_mshr_hits 311 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1138000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.091264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 187 # number of overall MSHR misses +system.cpu.dcache.overall_hits 1879 # number of overall hits +system.cpu.dcache.overall_miss_latency 3406000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.089632 # miss rate for overall accesses +system.cpu.dcache.overall_misses 185 # number of overall misses +system.cpu.dcache.overall_mshr_hits 314 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1131000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.089632 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,91 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 111.683956 # Cycle average of tags in use -system.cpu.dcache.total_refs 1876 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.245747 # Cycle average of tags in use +system.cpu.dcache.total_refs 1894 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 428 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 164 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11204 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5725 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1989 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 729 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchMispred 80 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 11542 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6127 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2070 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 788 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 235 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 36 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1984 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1520 # Number of cache lines fetched -system.cpu.fetch.Cycles 3641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12195 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 444 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.222746 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1520 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 813 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.369148 # Number of inst fetches per cycle +system.cpu.dtb.accesses 2656 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 2596 # DTB hits +system.cpu.dtb.misses 60 # DTB misses +system.cpu.dtb.read_accesses 1652 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1615 # DTB read hits +system.cpu.dtb.read_misses 37 # DTB read misses +system.cpu.dtb.write_accesses 1004 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 981 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.fetch.Branches 2029 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1542 # Number of cache lines fetched +system.cpu.fetch.Cycles 3746 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 226 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12519 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.214732 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1542 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.324902 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 8907 +system.cpu.fetch.rateDist.samples 9449 system.cpu.fetch.rateDist.min_value 0 - 0 6787 7619.85% - 1 178 199.84% - 2 167 187.49% - 3 149 167.28% - 4 210 235.77% - 5 157 176.27% - 6 180 202.09% - 7 101 113.39% - 8 978 1098.01% + 0 7275 7699.23% + 1 181 191.55% + 2 174 184.15% + 3 146 154.51% + 4 219 231.77% + 5 159 168.27% + 6 189 200.02% + 7 101 106.89% + 8 1005 1063.60% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1497 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7812.101911 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1183 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2453000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.209753 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 314 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1727000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.209753 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1520 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7745.954693 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5443.365696 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1211 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 2393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.203289 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 309 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1682000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.203289 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 309 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.767516 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.919094 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1497 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7812.101911 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5500 # average overall mshr miss latency -system.cpu.icache.demand_hits 1183 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2453000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.209753 # miss rate for demand accesses -system.cpu.icache.demand_misses 314 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1727000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.209753 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1520 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7745.954693 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency +system.cpu.icache.demand_hits 1211 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 2393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.203289 # miss rate for demand accesses +system.cpu.icache.demand_misses 309 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1682000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.203289 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 309 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1497 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7812.101911 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5500 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1520 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7745.954693 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1183 # number of overall hits -system.cpu.icache.overall_miss_latency 2453000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.209753 # miss rate for overall accesses -system.cpu.icache.overall_misses 314 # number of overall misses -system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1727000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.209753 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses +system.cpu.icache.overall_hits 1211 # number of overall hits +system.cpu.icache.overall_miss_latency 2393500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.203289 # miss rate for overall accesses +system.cpu.icache.overall_misses 309 # number of overall misses +system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1682000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.203289 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 309 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 309 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 165.376334 # Cycle average of tags in use -system.cpu.icache.total_refs 1183 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 164.253671 # Cycle average of tags in use +system.cpu.icache.total_refs 1211 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 88946 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1172 # Number of branches executed -system.cpu.iew.EXEC:nop 45 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.880207 # Inst execution rate -system.cpu.iew.EXEC:refs 2591 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 974 # Number of stores executed +system.cpu.idleCycles 110443 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1199 # Number of branches executed +system.cpu.iew.EXEC:nop 72 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.848450 # Inst execution rate +system.cpu.iew.EXEC:refs 2660 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1006 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5292 # num instructions consuming a value -system.cpu.iew.WB:count 7505 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745276 # average fanout of values written-back +system.cpu.iew.WB:consumers 5426 # num instructions consuming a value +system.cpu.iew.WB:count 7664 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742905 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3944 # num instructions producing a value -system.cpu.iew.WB:rate 0.842596 # insts written-back per cycle -system.cpu.iew.WB:sent 7591 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 4031 # num instructions producing a value +system.cpu.iew.WB:rate 0.811091 # insts written-back per cycle +system.cpu.iew.WB:sent 7781 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1979 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2030 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 194 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1190 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9672 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1617 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 358 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7840 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1236 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9996 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8017 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 729 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 788 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1000 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 378 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 66 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.631301 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.631301 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8198 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1051 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 424 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.595089 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.595089 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8383 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5452 66.50% # Type of FU issued + IntAlu 5559 66.31% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -279,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1744 21.27% # Type of FU issued - MemWrite 997 12.16% # Type of FU issued + MemRead 1786 21.31% # Type of FU issued + MemWrite 1033 12.32% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 102 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012442 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.012167 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 0 0.00% # attempts to use FU when none available + IntAlu 1 0.98% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,96 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 67 65.69% # attempts to use FU when none available + MemRead 66 64.71% # attempts to use FU when none available MemWrite 35 34.31% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 8907 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9449 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5630 6320.87% - 1 1096 1230.49% - 2 792 889.19% - 3 582 653.42% - 4 464 520.94% - 5 200 224.54% - 6 99 111.15% - 7 30 33.68% - 8 14 15.72% + 0 6104 6459.94% + 1 1119 1184.25% + 2 811 858.29% + 3 592 626.52% + 4 460 486.82% + 5 212 224.36% + 6 105 111.12% + 7 32 33.87% + 8 14 14.82% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.920400 # Inst issue rate -system.cpu.iq.iqInstsAdded 9604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8198 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.887184 # Inst issue rate +system.cpu.iq.iqInstsAdded 9901 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8383 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3664 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3948 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2365 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4486.301370 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2486.301370 # average ReadExReq mshr miss latency +system.cpu.iq.iqSquashedOperandsExamined 2574 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1572 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 1542 # ITB hits +system.cpu.itb.misses 30 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4548.611111 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2548.611111 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency 327500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 181500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 183500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 414 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4450.242718 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.242718 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1833500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995169 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1009500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995169 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4214.285714 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2214.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 59000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4400.246305 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2400.246305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1786500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 974500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4266.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2266.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 64000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 34000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 487 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4455.670103 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2161000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995893 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 479 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4422.594142 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2114000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997912 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 478 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1191000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995893 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1158000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 478 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 487 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4455.670103 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 479 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4422.594142 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2161000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995893 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2114000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997912 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 478 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1191000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995893 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1158000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 478 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -399,29 +415,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 221.319862 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 218.025629 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 8907 # number of cpu cycles simulated +system.cpu.numCycles 9449 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 5884 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 6291 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 13715 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10735 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8030 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1846 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 729 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 14101 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11035 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8205 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 788 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 122 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 3979 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 4154 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 276 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 532 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 54 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 57 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index fe297b10e..2c1517e04 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:40 2007 -M5 executing on zeep +M5 compiled Aug 13 2007 17:39:24 +M5 started Mon Aug 13 17:39:25 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4515000 because target called exit() +Exiting @ tick 4806000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index d025afdec..264bd19de 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,14 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.tracer] type=ExeTracer @@ -41,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index f87ad2cd6..c89057e77 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109073 # Simulator instruction rate (inst/s) -host_mem_usage 148564 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 54123810 # Simulator tick rate (ticks/s) +host_inst_rate 274181 # Simulator instruction rate (inst/s) +host_mem_usage 172576 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 135418658 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5642 # Number of instructions simulated +sim_insts 5641 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2820500 # Number of ticks simulated +sim_ticks 2833500 # Number of ticks simulated +system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.misses 10 # DTB misses +system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5642 # number of cpu cycles simulated -system.cpu.num_insts 5642 # Number of instructions executed -system.cpu.num_refs 1792 # Number of memory references +system.cpu.numCycles 5668 # number of cpu cycles simulated +system.cpu.num_insts 5641 # Number of instructions executed +system.cpu.num_refs 1801 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 0bec3d18f..9af7c0a45 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 03:56:47 -M5 started Fri Aug 3 04:17:12 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 17:36:58 +M5 started Tue Aug 14 17:40:03 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2820500 because target called exit() +Exiting @ tick 2833500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index c95e2e383..78fe6c01f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +166,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 3c7a26090..0908a82c9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 334797 # Simulator instruction rate (inst/s) -host_mem_usage 196348 # Number of bytes of host memory used +host_inst_rate 243703 # Simulator instruction rate (inst/s) +host_mem_usage 179944 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1064082508 # Simulator tick rate (ticks/s) +host_tick_rate 781539770 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5642 # Number of instructions simulated +sim_insts 5641 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18365000 # Number of ticks simulated +sim_ticks 18374000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.396682 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.386256 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.misses 10 # DTB misses +system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24956.678700 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 6359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.371841 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24956.678700 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency -system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits +system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 6359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24956.678700 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5366 # number of overall hits +system.cpu.icache.overall_hits 5375 # number of overall hits system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 6359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 128.096333 # Cycle average of tags in use -system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 128.084203 # Cycle average of tags in use +system.cpu.icache.total_refs 5375 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 5669 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 5652 # ITB hits +system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -219,14 +235,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 177.517189 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.499846 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18365000 # number of cpu cycles simulated -system.cpu.num_insts 5642 # Number of instructions executed -system.cpu.num_refs 1792 # Number of memory references +system.cpu.numCycles 18374000 # number of cpu cycles simulated +system.cpu.num_insts 5641 # Number of instructions executed +system.cpu.num_refs 1801 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 940c4ad1c..67d82b1c5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:41 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 17:58:14 +M5 started Tue Aug 14 17:59:07 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 18365000 because target called exit() +Exiting @ tick 18374000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index f5eb9b8b9..d3406f49b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 536bed0d1..ffd2f7ab7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 143 # Number of BTB hits -global.BPredUnit.BTBLookups 610 # Number of BTB lookups -global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 394 # Number of conditional branches predicted -global.BPredUnit.lookups 779 # Number of BP lookups -global.BPredUnit.usedRAS 155 # Number of times the RAS was used to get a target. -host_inst_rate 72558 # Simulator instruction rate (inst/s) -host_mem_usage 196048 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 63572637 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. +global.BPredUnit.BTBHits 156 # Number of BTB hits +global.BPredUnit.BTBLookups 642 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 213 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 401 # Number of conditional branches predicted +global.BPredUnit.lookups 824 # Number of BP lookups +global.BPredUnit.usedRAS 163 # Number of times the RAS was used to get a target. +host_inst_rate 31893 # Simulator instruction rate (inst/s) +host_mem_usage 179460 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 32096529 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 636 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 698 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 412 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2104000 # Number of ticks simulated +sim_ticks 2410000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 32 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 3945 +system.cpu.commit.COM:committed_per_cycle.samples 4452 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 2992 7584.28% - 1 255 646.39% - 2 335 849.18% - 3 139 352.34% - 4 66 167.30% - 5 69 174.90% - 6 33 83.65% - 7 21 53.23% - 8 35 88.72% + 0 3490 7839.17% + 1 258 579.51% + 2 340 763.70% + 3 140 314.47% + 4 70 157.23% + 5 70 157.23% + 6 32 71.88% + 7 20 44.92% + 8 32 71.88% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1134 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1380 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.747382 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.747382 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 519 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8729.508197 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5745.901639 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 532500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.117534 # miss rate for ReadReq accesses +system.cpu.cpi 1.984080 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.984080 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 8639.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5655.737705 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 467 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 527000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.115530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 350500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.117534 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 345000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.115530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 18810.810811 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6202.702703 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 18297.297297 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5986.486486 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 696000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 677000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 229500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 221500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 7.929412 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.035294 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 759 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 12535.714286 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency -system.cpu.dcache.demand_hits 661 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1228500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.129117 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 768 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 12285.714286 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency +system.cpu.dcache.demand_hits 670 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1204000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127604 # miss rate for demand accesses system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.129117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 566500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.127604 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 759 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 12535.714286 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 768 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 12285.714286 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 661 # number of overall hits -system.cpu.dcache.overall_miss_latency 1228500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.129117 # miss rate for overall accesses +system.cpu.dcache.overall_hits 670 # number of overall hits +system.cpu.dcache.overall_miss_latency 1204000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127604 # miss rate for overall accesses system.cpu.dcache.overall_misses 98 # number of overall misses system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 580000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.129117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 566500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.127604 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 50.690606 # Cycle average of tags in use -system.cpu.dcache.total_refs 674 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 47.072215 # Cycle average of tags in use +system.cpu.dcache.total_refs 683 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 91 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 93 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 126 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4236 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 809 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BranchResolved 135 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4564 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3475 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 303 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 779 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 691 # Number of cache lines fetched -system.cpu.fetch.Cycles 1534 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 112 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 4961 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.186766 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 691 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 298 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.189403 # Number of inst fetches per cycle +system.cpu.dtb.accesses 931 # DTB accesses +system.cpu.dtb.acv 1 # DTB access violations +system.cpu.dtb.hits 904 # DTB hits +system.cpu.dtb.misses 27 # DTB misses +system.cpu.dtb.read_accesses 575 # DTB read accesses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_hits 563 # DTB read hits +system.cpu.dtb.read_misses 12 # DTB read misses +system.cpu.dtb.write_accesses 356 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 341 # DTB write hits +system.cpu.dtb.write_misses 15 # DTB write misses +system.cpu.fetch.Branches 824 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 707 # Number of cache lines fetched +system.cpu.fetch.Cycles 1626 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5268 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 242 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.173986 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 707 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 319 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.112331 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 4171 +system.cpu.fetch.rateDist.samples 4736 system.cpu.fetch.rateDist.min_value 0 - 0 3330 7983.70% - 1 36 86.31% - 2 85 203.79% - 3 57 136.66% - 4 109 261.33% - 5 54 129.47% - 6 40 95.90% - 7 42 100.70% - 8 418 1002.16% + 0 3845 8118.67% + 1 38 80.24% + 2 85 179.48% + 3 63 133.02% + 4 118 249.16% + 5 55 116.13% + 6 42 88.68% + 7 48 101.35% + 8 442 933.28% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 674 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7774.193548 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5451.612903 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 488 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.275964 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1014000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.275964 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7648.351648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5370.879121 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 510 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1392000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.263006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 182 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 977500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.263006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.623656 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.802198 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 674 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7774.193548 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency -system.cpu.icache.demand_hits 488 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.275964 # miss rate for demand accesses -system.cpu.icache.demand_misses 186 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1014000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.275964 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 692 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7648.351648 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency +system.cpu.icache.demand_hits 510 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1392000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.263006 # miss rate for demand accesses +system.cpu.icache.demand_misses 182 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 977500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.263006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 674 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7774.193548 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency +system.cpu.icache.overall_accesses 692 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7648.351648 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 488 # number of overall hits -system.cpu.icache.overall_miss_latency 1446000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.275964 # miss rate for overall accesses -system.cpu.icache.overall_misses 186 # number of overall misses -system.cpu.icache.overall_mshr_hits 17 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1014000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.275964 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses +system.cpu.icache.overall_hits 510 # number of overall hits +system.cpu.icache.overall_miss_latency 1392000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.263006 # miss rate for overall accesses +system.cpu.icache.overall_misses 182 # number of overall misses +system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 977500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.263006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 102.643576 # Cycle average of tags in use -system.cpu.icache.total_refs 488 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.900452 # Cycle average of tags in use +system.cpu.icache.total_refs 510 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 26984 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 522 # Number of branches executed -system.cpu.iew.EXEC:nop 242 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.736514 # Inst execution rate -system.cpu.iew.EXEC:refs 896 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 333 # Number of stores executed +system.cpu.idleCycles 56472 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 538 # Number of branches executed +system.cpu.iew.EXEC:nop 274 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.670608 # Inst execution rate +system.cpu.iew.EXEC:refs 934 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 356 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1736 # num instructions consuming a value -system.cpu.iew.WB:count 3002 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.793779 # average fanout of values written-back +system.cpu.iew.WB:consumers 1781 # num instructions consuming a value +system.cpu.iew.WB:count 3084 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.794497 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1378 # num instructions producing a value -system.cpu.iew.WB:rate 0.719731 # insts written-back per cycle -system.cpu.iew.WB:sent 3020 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 147 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1415 # num instructions producing a value +system.cpu.iew.WB:rate 0.651182 # insts written-back per cycle +system.cpu.iew.WB:sent 3123 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 149 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 636 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 698 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 3727 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 563 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 108 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3072 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 412 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4056 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 578 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 105 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3176 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 225 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 221 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.572285 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.572285 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3180 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 283 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 118 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.504012 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.504012 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3281 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 2258 71.01% # Type of FU issued + IntAlu 2319 70.68% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -279,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 581 18.27% # Type of FU issued - MemWrite 340 10.69% # Type of FU issued + MemRead 597 18.20% # Type of FU issued + MemWrite 364 11.09% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 36 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011321 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010667 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2 5.56% # attempts to use FU when none available + IntAlu 1 2.86% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,59 +309,63 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 12 33.33% # attempts to use FU when none available - MemWrite 22 61.11% # attempts to use FU when none available + MemRead 12 34.29% # attempts to use FU when none available + MemWrite 22 62.86% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 4171 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4736 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2877 6897.63% - 1 465 1114.84% - 2 300 719.25% - 3 228 546.63% - 4 154 369.22% - 5 89 213.38% - 6 40 95.90% - 7 14 33.57% - 8 4 9.59% + 0 3384 7145.27% + 1 494 1043.07% + 2 314 663.01% + 3 237 500.42% + 4 163 344.17% + 5 88 185.81% + 6 40 84.46% + 7 12 25.34% + 8 4 8.45% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.762407 # Inst issue rate -system.cpu.iq.iqInstsAdded 3479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3180 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.692779 # Inst issue rate +system.cpu.iq.iqInstsAdded 3776 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3281 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 944 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 1238 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 473 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 742 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 735 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 707 # ITB hits +system.cpu.itb.misses 28 # ITB misses system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4750 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2750 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 114000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4604.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2604.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 66000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 62500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 247 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4354.251012 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2354.251012 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1075500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4304.526749 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2304.526749 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1046000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 247 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 581500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 560000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 247 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2250 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 59500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4178.571429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2178.571429 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 58500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 30500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -360,32 +376,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4389.298893 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4331.460674 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1189500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1156500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 647500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 622500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4389.298893 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4331.460674 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1189500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1156500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 271 # number of overall misses +system.cpu.l2cache.overall_misses 267 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 647500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 622500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -398,28 +414,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 127.304233 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 115.687599 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 4171 # number of cpu cycles simulated +system.cpu.numCycles 4736 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3117 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4657 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4106 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2936 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 738 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1168 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IdleCycles 3552 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4989 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4410 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3154 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 808 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 283 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1386 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 50 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 28 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 57159efac..895bd710c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:41 2007 -M5 executing on zeep +M5 compiled Aug 13 2007 17:39:24 +M5 started Mon Aug 13 17:39:27 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2104000 because target called exit() +Exiting @ tick 2410000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 16ea738bc..ac0ec32b8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,14 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.tracer] type=ExeTracer @@ -41,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index dfc8b7f6b..28ff448c6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 34280 # Simulator instruction rate (inst/s) -host_mem_usage 147884 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 17043200 # Simulator tick rate (ticks/s) +host_inst_rate 124133 # Simulator instruction rate (inst/s) +host_mem_usage 171628 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 61574601 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2578 # Number of instructions simulated +sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1288500 # Number of ticks simulated +sim_ticks 1297500 # Number of ticks simulated +system.cpu.dtb.accesses 717 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 709 # DTB hits +system.cpu.dtb.misses 8 # DTB misses +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2596 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2585 # ITB hits +system.cpu.itb.misses 11 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2578 # number of cpu cycles simulated -system.cpu.num_insts 2578 # Number of instructions executed -system.cpu.num_refs 710 # Number of memory references +system.cpu.numCycles 2596 # number of cpu cycles simulated +system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 6e78c47eb..89de75b41 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 03:56:47 -M5 started Fri Aug 3 04:17:14 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 17:36:58 +M5 started Tue Aug 14 17:40:04 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1288500 because target called exit() +Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index f8e125ea1..48fcc2b94 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +166,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 23e886f55..942cc1b79 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 196854 # Simulator instruction rate (inst/s) -host_mem_usage 195480 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 706389035 # Simulator tick rate (ticks/s) +host_inst_rate 123219 # Simulator instruction rate (inst/s) +host_mem_usage 178996 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 443932267 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2578 # Number of instructions simulated +sim_insts 2577 # Number of instructions simulated sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9431000 # Number of ticks simulated +sim_ticks 9438000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 48.863963 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 48.838317 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 717 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 709 # DTB hits +system.cpu.dtb.misses 8 # DTB misses +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency -system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2416 # number of overall hits +system.cpu.icache.overall_hits 2423 # number of overall hits system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 83.443652 # Cycle average of tags in use -system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 83.395749 # Cycle average of tags in use +system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2597 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2586 # ITB hits +system.cpu.itb.misses 11 # ITB misses system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -218,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 106.620093 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 106.559981 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9431000 # number of cpu cycles simulated -system.cpu.num_insts 2578 # Number of instructions executed -system.cpu.num_refs 710 # Number of memory references +system.cpu.numCycles 9438000 # number of cpu cycles simulated +system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index eb8910969..8d08b94be 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:42 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 17:58:14 +M5 started Tue Aug 14 17:59:08 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 9431000 because target called exit() +Exiting @ tick 9438000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index c6807e6a7..653ab3552 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,12 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=MipsDTB + +[system.cpu.itb] +type=MipsITB + [system.cpu.tracer] type=ExeTracer @@ -41,7 +49,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 98d540d90..23e6b5f2c 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 25511 # Simulator instruction rate (inst/s) -host_mem_usage 149560 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -host_tick_rate 12728361 # Simulator tick rate (ticks/s) +host_inst_rate 9753 # Simulator instruction rate (inst/s) +host_mem_usage 173424 # Number of bytes of host memory used +host_seconds 0.58 # Real time elapsed on the host +host_tick_rate 4872477 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5657 # Number of instructions simulated +sim_insts 5656 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated sim_ticks 2828000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5657 # number of cpu cycles simulated -system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 3919c7c81..1cc3f6662 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 04:06:41 -M5 started Fri Aug 3 04:31:09 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:02:23 +M5 started Tue Aug 14 22:02:24 2007 +M5 executing on nacho command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index f2dee3856..7da6cb048 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,9 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=MipsDTB + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +106,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=MipsITB + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +164,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index a9c46636a..cb408c2ca 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 269189 # Simulator instruction rate (inst/s) -host_mem_usage 197500 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 866482072 # Simulator tick rate (ticks/s) +host_inst_rate 186969 # Simulator instruction rate (inst/s) +host_mem_usage 180780 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 602814418 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5657 # Number of instructions simulated +sim_insts 5656 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated sim_ticks 18463000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) @@ -225,7 +225,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 18463000 # number of cpu cycles simulated -system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index ad6e002b5..08628c4d1 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 17:11:48 -M5 started Sun Aug 12 17:11:50 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:02:23 +M5 started Tue Aug 14 22:02:25 2007 +M5 executing on nacho command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 18463000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index d7237a4af..c019a4e06 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,14 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.tracer] type=ExeTracer @@ -41,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index ab2e76d2a..5a17e8489 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 15625 # Simulator instruction rate (inst/s) -host_mem_usage 149968 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 7799892 # Simulator tick rate (ticks/s) +host_inst_rate 5187 # Simulator instruction rate (inst/s) +host_mem_usage 173740 # Number of bytes of host memory used +host_seconds 0.93 # Real time elapsed on the host +host_tick_rate 2625893 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4863 # Number of instructions simulated +sim_insts 4833 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2431000 # Number of ticks simulated +sim_ticks 2447500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4863 # number of cpu cycles simulated -system.cpu.num_insts 4863 # Number of instructions executed -system.cpu.num_refs 1269 # Number of memory references +system.cpu.numCycles 4896 # number of cpu cycles simulated +system.cpu.num_insts 4833 # Number of instructions executed +system.cpu.num_refs 1282 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 40d1acccc..5bc4aa638 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 04:11:25 -M5 started Fri Aug 3 04:31:18 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:22 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2431000 because target called exit() +Exiting @ tick 2447500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 719701ccd..4674f8812 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +166,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 8907d716d..ff4bd3dbe 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 277220 # Simulator instruction rate (inst/s) -host_mem_usage 197684 # Number of bytes of host memory used +host_inst_rate 198489 # Simulator instruction rate (inst/s) +host_mem_usage 181156 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 892278360 # Simulator tick rate (ticks/s) +host_tick_rate 645076356 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4863 # Number of instructions simulated +sim_insts 4833 # Number of instructions simulated sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15912000 # Number of ticks simulated +sim_ticks 15925000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency @@ -76,53 +76,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.464621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.440192 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency -system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits +system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4608 # number of overall hits +system.cpu.icache.overall_hits 4621 # number of overall hits system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.953503 # Cycle average of tags in use -system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 114.921642 # Cycle average of tags in use +system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -219,14 +219,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.743977 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 133.706132 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15912000 # number of cpu cycles simulated -system.cpu.num_insts 4863 # Number of instructions executed -system.cpu.num_refs 1269 # Number of memory references +system.cpu.numCycles 15925000 # number of cpu cycles simulated +system.cpu.num_insts 4833 # Number of instructions executed +system.cpu.num_refs 1282 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 85df476d4..d947b5fb6 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 12:23:15 -M5 started Sun Aug 12 16:58:40 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:24 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 15912000 because target called exit() +Exiting @ tick 15925000 because target called exit() |