diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:23 -0800 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:23 -0800 |
| commit | d1dd7a24dbeec44a5de232549fa863ff597be349 (patch) | |
| tree | 83755e42e7507fd86f6f573d13570118dec9549e /tests/quick/00.hello | |
| parent | 61c14da751ae80e8c19e0b63ddd629c4152f1c72 (diff) | |
| download | gem5-d1dd7a24dbeec44a5de232549fa863ff597be349.tar.xz | |
imported patch ext/stats_updates.patch
--HG--
extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
Diffstat (limited to 'tests/quick/00.hello')
| -rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 648 |
3 files changed, 330 insertions, 330 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 6ed416710..35f7f2ba7 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index d350ca8e5..2cb4f1a9c 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 13:15:14 -gem5 executing on zizzer -command line: ./build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 19:01:51 +gem5 executing on u200540-lin +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 9807000 because target called exit() +Exiting @ tick 10001500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 5bb9beb5c..3aaa40ec4 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 9807000 # Number of ticks simulated +sim_ticks 10001500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16610 # Simulator instruction rate (inst/s) -host_tick_rate 28382842 # Simulator tick rate (ticks/s) -host_mem_usage 221852 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host +host_inst_rate 48143 # Simulator instruction rate (inst/s) +host_tick_rate 83889434 # Simulator tick rate (ticks/s) +host_mem_usage 212568 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,244 +51,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 19615 # number of cpu cycles simulated +system.cpu.numCycles 20004 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2510 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1858 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1876 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 752 # Number of BTB hits +system.cpu.BPredUnit.lookups 2398 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6260 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12668 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2510 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1020 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1646 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1029 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.423992 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.773203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1920 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.338054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.716635 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8435 74.90% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.43% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 191 1.70% 79.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 2.18% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 240 2.13% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 319 2.83% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 123 1.09% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 122 1.08% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1312 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8816 76.59% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.95% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.97% 84.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 313 2.72% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127963 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.645832 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6543 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1078 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2628 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 952 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14071 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 952 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6829 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2400 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 182 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13225 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12790 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 60358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 59038 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 11510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119876 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.606579 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6265 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2491 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6541 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2270 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7101 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 440 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2690 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1760 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 41 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11414 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5140 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13918 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.824188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485862 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.438063 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7565 67.17% 67.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.85% 79.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 849 7.54% 86.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 557 4.95% 91.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 476 4.23% 95.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.47% 98.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 148 1.31% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.38% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8025 69.72% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11510 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.75% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 141 64.68% 67.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 32.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5672 61.11% 61.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2322 25.02% 86.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1278 13.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9282 # Type of FU issued -system.cpu.iq.rate 0.473209 # Inst issue rate -system.cpu.iq.fu_busy_cnt 218 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023486 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30073 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16544 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8314 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 8706 # Type of FU issued +system.cpu.iq.rate 0.435213 # Inst issue rate +system.cpu.iq.fu_busy_cnt 203 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29184 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 952 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11442 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 210 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2690 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1760 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 301 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 397 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8848 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2122 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 434 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_refs 3344 # number of memory reference insts executed -system.cpu.iew.exec_branches 1461 # Number of branches executed -system.cpu.iew.exec_stores 1222 # Number of stores executed -system.cpu.iew.exec_rate 0.451083 # Inst execution rate -system.cpu.iew.wb_sent 8506 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8330 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3963 # num instructions producing a value -system.cpu.iew.wb_consumers 7807 # num instructions consuming a value +system.cpu.iew.exec_nop 1 # number of nop insts executed +system.cpu.iew.exec_refs 3178 # number of memory reference insts executed +system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_stores 1169 # Number of stores executed +system.cpu.iew.exec_rate 0.414017 # Inst execution rate +system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7840 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3690 # num instructions producing a value +system.cpu.iew.wb_consumers 7291 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.424675 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.507621 # average fanout of values written-back +system.cpu.iew.wb_rate 0.391922 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5548 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.556590 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.365529 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.540192 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.352731 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7969 77.29% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1090 10.57% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 425 4.12% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 280 2.72% 94.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.77% 96.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 171 1.66% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.65% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 38 0.37% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8288 78.01% 78.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.95% 92.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10624 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed @@ -298,49 +298,49 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21353 # The number of ROB reads -system.cpu.rob.rob_writes 23544 # The number of ROB writes +system.cpu.rob.rob_reads 21207 # The number of ROB reads +system.cpu.rob.rob_writes 22566 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.417843 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.417843 # CPI: Total CPI of All Threads -system.cpu.ipc 0.292582 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.292582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40279 # number of integer regfile reads -system.cpu.int_regfile_writes 8179 # number of integer regfile writes -system.cpu.fp_regfile_reads 29 # number of floating regfile reads -system.cpu.misc_regfile_reads 15700 # number of misc regfile reads +system.cpu.cpi 3.485625 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.485625 # CPI: Total CPI of All Threads +system.cpu.ipc 0.286893 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.286893 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 37816 # number of integer regfile reads +system.cpu.int_regfile_writes 7658 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.misc_regfile_reads 14993 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 150.950866 # Cycle average of tags in use -system.cpu.icache.total_refs 1667 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.631757 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 148.864335 # Cycle average of tags in use +system.cpu.icache.total_refs 1560 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.252525 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 150.950866 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.073706 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1667 # number of ReadReq hits -system.cpu.icache.demand_hits 1667 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1667 # number of overall hits -system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses -system.cpu.icache.demand_misses 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.179222 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.179222 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.179222 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34663.461538 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34663.461538 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34663.461538 # average overall miss latency +system.cpu.icache.occ_blocks::0 148.864335 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.072688 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1560 # number of ReadReq hits +system.cpu.icache.demand_hits 1560 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1560 # number of overall hits +system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.icache.demand_misses 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1920 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1920 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.187500 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.187500 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.187500 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,67 +350,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9940000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9940000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9940000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33581.081081 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.154688 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.154688 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.154688 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.326406 # Cycle average of tags in use -system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.500000 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.089443 # Cycle average of tags in use +system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.326406 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022541 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1789 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 89.089443 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021750 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 2398 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2398 # number of overall hits -system.cpu.dcache.ReadReq_misses 177 # number of ReadReq misses +system.cpu.dcache.demand_hits 2311 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2311 # number of overall hits +system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 481 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5493500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 473 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10725000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 16199000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16199000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 16075500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16075500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1871 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.090031 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2784 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2784 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.090326 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.167072 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167072 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31036.723164 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.169899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.169899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31659.763314 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35279.605263 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33677.754678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33677.754678 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33986.257928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33986.257928 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,64 +420,64 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 325 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 112 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4735000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4735000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.057986 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.059861 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.054185 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.054185 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.055316 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.055316 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 191.048911 # Cycle average of tags in use -system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.120549 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 191.048911 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005830 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits -system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 43 # number of overall hits +system.cpu.l2cache.occ_blocks::0 188.120549 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits +system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 42 # number of overall hits system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12611500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14062000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14062000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency 12613500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1452000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 14065500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14065500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 452 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.895122 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.897311 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34363.760218 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34381.418093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34381.418093 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.906874 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.906874 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34389.975550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34389.975550 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,17 +495,17 @@ system.cpu.l2cache.ReadExReq_mshr_misses 42 # nu system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11306000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11304000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1319000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885086 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31232.044199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.895787 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.895787 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency |