diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
| commit | f125ef22b997d5ba6173d9d3f0d07ae741e279bd (patch) | |
| tree | d3d103939211116d7f8ed7e04db73fbac0b9e9be /tests/quick/00.hello | |
| parent | d0e04859023702ec23c97683700c638949a1dad1 (diff) | |
| download | gem5-f125ef22b997d5ba6173d9d3f0d07ae741e279bd.tar.xz | |
O3: Update stats for LSQ changes.
Diffstat (limited to 'tests/quick/00.hello')
12 files changed, 1578 insertions, 1579 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index f022a446d..fa9debdd1 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 15:20:58 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 20:03:54 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12002500 because target called exit() +Exiting @ tick 12003500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 50d6ec22a..a8b7869e5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12002500 # Number of ticks simulated +sim_ticks 12003500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25819 # Simulator instruction rate (inst/s) -host_tick_rate 48521023 # Simulator tick rate (ticks/s) -host_mem_usage 243716 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 47992 # Simulator instruction rate (inst/s) +host_tick_rate 90187460 # Simulator tick rate (ticks/s) +host_mem_usage 243780 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1863 # DTB read hits +system.cpu.dtb.read_hits 1860 # DTB read hits system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1908 # DTB read accesses -system.cpu.dtb.write_hits 1047 # DTB write hits +system.cpu.dtb.read_accesses 1905 # DTB read accesses +system.cpu.dtb.write_hits 1043 # DTB write hits system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1075 # DTB write accesses -system.cpu.dtb.data_hits 2910 # DTB hits +system.cpu.dtb.write_accesses 1071 # DTB write accesses +system.cpu.dtb.data_hits 2903 # DTB hits system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2983 # DTB accesses -system.cpu.itb.fetch_hits 2044 # ITB hits +system.cpu.dtb.data_accesses 2976 # DTB accesses +system.cpu.itb.fetch_hits 2041 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2073 # ITB accesses +system.cpu.itb.fetch_accesses 2070 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,102 +41,102 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24006 # number of cpu cycles simulated +system.cpu.numCycles 24008 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2516 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1462 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1456 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1947 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 723 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1935 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 719 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7155 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14481 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2516 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1095 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2626 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1554 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14447 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1092 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1555 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2044 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.149103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.531397 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2041 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.147407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.529389 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9976 79.16% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.17% 81.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 231 1.83% 83.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 220 1.75% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 235 1.86% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 176 1.40% 88.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.04% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.12% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1092 8.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9972 79.20% 79.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 273 2.17% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 226 1.79% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.76% 84.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 235 1.87% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 177 1.41% 88.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 258 2.05% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.12% 91.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1087 8.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104807 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.603224 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7976 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 12591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104340 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.601758 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7971 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2455 # Number of cycles decode is running +system.cpu.decode.RunCycles 2448 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 976 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 216 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 977 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13403 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13375 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8164 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 977 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2326 # Number of cycles rename is running +system.cpu.rename.RunCycles 2318 # Number of cycles rename is running system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12866 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12830 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9599 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16086 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16069 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9571 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16046 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16029 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5016 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4988 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2397 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1265 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2392 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1263 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11550 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9768 # Number of instructions issued +system.cpu.iq.iqInstsIssued 9758 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4900 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2850 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4875 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2832 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.775115 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397410 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12591 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.774998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.396796 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8516 67.58% 67.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1470 11.66% 79.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1066 8.46% 87.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 684 5.43% 93.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 441 3.50% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.02% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8508 67.57% 67.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1466 11.64% 79.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1070 8.50% 87.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 438 3.48% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 253 2.01% 98.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12591 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available @@ -172,114 +172,114 @@ system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6583 67.39% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2078 21.27% 88.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1102 11.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6577 67.40% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2074 21.25% 88.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 11.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9768 # Type of FU issued -system.cpu.iq.rate 0.406898 # Inst issue rate +system.cpu.iq.FU_type_0::total 9758 # Type of FU issued +system.cpu.iq.rate 0.406448 # Inst issue rate system.cpu.iq.fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010749 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32267 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16511 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8987 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010760 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32236 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16459 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8983 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9860 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1212 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1207 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 400 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 398 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 976 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 977 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11685 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2397 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1265 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11657 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2392 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1263 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 445 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9324 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1918 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 446 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9316 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1915 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 2995 # number of memory reference insts executed -system.cpu.iew.exec_branches 1503 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.388403 # Inst execution rate -system.cpu.iew.wb_sent 9127 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8997 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4717 # num instructions producing a value -system.cpu.iew.wb_consumers 6401 # num instructions consuming a value +system.cpu.iew.exec_refs 2988 # number of memory reference insts executed +system.cpu.iew.exec_branches 1504 # Number of branches executed +system.cpu.iew.exec_stores 1073 # Number of stores executed +system.cpu.iew.exec_rate 0.388037 # Inst execution rate +system.cpu.iew.wb_sent 9122 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8993 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4720 # num instructions producing a value +system.cpu.iew.wb_consumers 6405 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374781 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736916 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374583 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736924 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5279 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5251 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11626 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.550748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.411308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.413328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8945 76.94% 76.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1414 12.16% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 463 3.98% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 244 2.10% 95.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 156 1.34% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 87 0.75% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.95% 98.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.38% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 241 2.08% 95.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 158 1.36% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.39% 98.60% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle system.cpu.commit.count 6403 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed @@ -291,48 +291,48 @@ system.cpu.commit.int_insts 6321 # Nu system.cpu.commit.function_calls 127 # Number of function calls committed. system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22794 # The number of ROB reads -system.cpu.rob.rob_writes 24351 # The number of ROB writes +system.cpu.rob.rob_reads 22754 # The number of ROB reads +system.cpu.rob.rob_writes 24296 # The number of ROB writes system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11417 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.759161 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.759161 # CPI: Total CPI of All Threads -system.cpu.ipc 0.266017 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.266017 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11850 # number of integer regfile reads -system.cpu.int_regfile_writes 6735 # number of integer regfile writes +system.cpu.cpi 3.759474 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759474 # CPI: Total CPI of All Threads +system.cpu.ipc 0.265995 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265995 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11838 # number of integer regfile reads +system.cpu.int_regfile_writes 6732 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.654959 # Cycle average of tags in use -system.cpu.icache.total_refs 1612 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 159.648657 # Cycle average of tags in use +system.cpu.icache.total_refs 1609 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.183280 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.173633 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 159.654959 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.077957 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1612 # number of ReadReq hits -system.cpu.icache.demand_hits 1612 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1612 # number of overall hits +system.cpu.icache.occ_blocks::0 159.648657 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077953 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1609 # number of ReadReq hits +system.cpu.icache.demand_hits 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1609 # number of overall hits system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses system.cpu.icache.demand_misses 432 # number of demand (read+write) misses system.cpu.icache.overall_misses 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15402000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15402000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15402000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2044 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2044 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2044 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.211350 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.211350 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.211350 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35652.777778 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35652.777778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35652.777778 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 15393500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15393500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15393500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2041 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.211661 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.211661 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.211661 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35633.101852 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35633.101852 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35633.101852 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,52 +349,52 @@ system.cpu.icache.ReadReq_mshr_misses 311 # nu system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10985500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10985500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10985500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10986500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10986500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10986500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.152153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.152153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.152153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.152376 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.152376 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.152376 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35326.366559 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.289403 # Cycle average of tags in use -system.cpu.dcache.total_refs 2155 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.288630 # Cycle average of tags in use +system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.385057 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.289403 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 109.288630 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2155 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2155 # number of overall hits -system.cpu.dcache.ReadReq_misses 155 # number of ReadReq misses +system.cpu.dcache.demand_hits 2154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2154 # number of overall hits +system.cpu.dcache.ReadReq_misses 154 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5502500 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5497000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17970000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17970000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1801 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 17964500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17964500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.086063 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2664 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.085603 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.191673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.191673 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35694.805195 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35166.340509 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35166.340509 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35224.509804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35224.509804 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,10 +404,10 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 336 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses @@ -418,10 +418,10 @@ system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056080 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.065266 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.065266 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency @@ -431,12 +431,12 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.186144 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.178797 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.186144 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 221.178797 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits @@ -445,10 +445,10 @@ system.cpu.l2cache.ReadReq_misses 411 # nu system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 484 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14129000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16641500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 16642500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16642500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses @@ -457,10 +457,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997573 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34377.128954 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34383.264463 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34383.264463 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34385.330579 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34385.330579 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 74424d63b..b62422ecd 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 15:21:09 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 20:04:15 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6921000 because target called exit() +Exiting @ tick 6833000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 5e52ef944..886aae88f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6921000 # Number of ticks simulated +sim_ticks 6833000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33894 # Simulator instruction rate (inst/s) -host_tick_rate 98227338 # Simulator tick rate (ticks/s) -host_mem_usage 242788 # Number of bytes of host memory used +host_inst_rate 36521 # Simulator instruction rate (inst/s) +host_tick_rate 104491306 # Simulator tick rate (ticks/s) +host_mem_usage 242860 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 720 # DTB read hits -system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_hits 679 # DTB read hits +system.cpu.dtb.read_misses 26 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 754 # DTB read accesses -system.cpu.dtb.write_hits 354 # DTB write hits -system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.read_accesses 705 # DTB read accesses +system.cpu.dtb.write_hits 356 # DTB write hits +system.cpu.dtb.write_misses 18 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 376 # DTB write accesses -system.cpu.dtb.data_hits 1074 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.write_accesses 374 # DTB write accesses +system.cpu.dtb.data_hits 1035 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1130 # DTB accesses -system.cpu.itb.fetch_hits 976 # ITB hits +system.cpu.dtb.data_accesses 1079 # DTB accesses +system.cpu.itb.fetch_hits 945 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1006 # ITB accesses +system.cpu.itb.fetch_accesses 975 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,245 +41,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13843 # number of cpu cycles simulated +system.cpu.numCycles 13667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1112 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 583 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 236 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 781 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 240 # Number of BTB hits +system.cpu.BPredUnit.lookups 1041 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 733 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 220 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6697 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1112 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 455 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1166 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 814 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 253 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 3751 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6413 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1041 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 430 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 754 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 781 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 976 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 159 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.021351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.437035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 945 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 157 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.004700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.420463 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5391 82.22% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 67 1.02% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 1.88% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 97 1.48% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 146 2.23% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 50 0.76% 89.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 61 0.93% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 83 1.27% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 539 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5268 82.53% 82.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60 0.94% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 118 1.85% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 94 1.47% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 140 2.19% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 58 0.91% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.86% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 1.02% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080329 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.483782 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4673 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 269 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1132 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 476 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 152 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076169 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.469232 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1083 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 426 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6020 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5734 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 476 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4772 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 89 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4737 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1039 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5743 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 11 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4153 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6495 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6483 # Number of integer rename lookups +system.cpu.rename.RunCycles 997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5480 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 3945 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6160 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6148 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2385 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2177 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 961 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 458 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4659 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3996 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2355 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1179 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6557 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.609425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.316967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608178 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.298400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4952 75.52% 75.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 578 8.82% 84.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 360 5.49% 89.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 270 4.12% 93.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 209 3.19% 97.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 109 1.66% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 54 0.82% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17 0.26% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4812 75.39% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 543 8.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6557 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.27% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20 45.45% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2819 70.55% 70.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 794 19.87% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 382 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2767 71.28% 71.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 734 18.91% 90.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3996 # Type of FU issued -system.cpu.iq.rate 0.288666 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011011 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14670 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7267 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3636 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3882 # Type of FU issued +system.cpu.iq.rate 0.284042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 41 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010562 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14224 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6793 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4033 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3916 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 546 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 164 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 476 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 79 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5242 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 961 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 458 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5003 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 137 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3843 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 133 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 329 # number of nop insts executed -system.cpu.iew.exec_refs 1131 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 376 # Number of stores executed -system.cpu.iew.exec_rate 0.277613 # Inst execution rate -system.cpu.iew.wb_sent 3725 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3642 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1733 # num instructions producing a value -system.cpu.iew.wb_consumers 2231 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1080 # number of memory reference insts executed +system.cpu.iew.exec_branches 629 # Number of branches executed +system.cpu.iew.exec_stores 374 # Number of stores executed +system.cpu.iew.exec_rate 0.274310 # Inst execution rate +system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3579 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1702 # num instructions producing a value +system.cpu.iew.wb_consumers 2165 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.263093 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776782 # average fanout of values written-back +system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2657 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 159 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.423615 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.271187 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 5957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.432432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.291215 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5177 85.13% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 230 3.78% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 323 5.31% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 118 1.94% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 1.10% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 52 0.86% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 37 0.61% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.33% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 57 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5066 85.04% 85.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 221 3.71% 88.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 314 5.27% 94.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 118 1.98% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 71 1.19% 97.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 5957 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 709 # Number of memory references committed @@ -289,49 +288,49 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 57 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11010 # The number of ROB reads -system.cpu.rob.rob_writes 10947 # The number of ROB writes +system.cpu.rob.rob_reads 10644 # The number of ROB reads +system.cpu.rob.rob_writes 10417 # The number of ROB writes system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.799330 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.799330 # CPI: Total CPI of All Threads -system.cpu.ipc 0.172434 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.172434 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4649 # number of integer regfile reads -system.cpu.int_regfile_writes 2817 # number of integer regfile writes +system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4520 # number of integer regfile reads +system.cpu.int_regfile_writes 2768 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.452549 # Cycle average of tags in use -system.cpu.icache.total_refs 735 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use +system.cpu.icache.total_refs 704 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.972973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.805405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 92.452549 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.045143 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 735 # number of ReadReq hits -system.cpu.icache.demand_hits 735 # number of demand (read+write) hits -system.cpu.icache.overall_hits 735 # number of overall hits +system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 704 # number of ReadReq hits +system.cpu.icache.demand_hits 704 # number of demand (read+write) hits +system.cpu.icache.overall_hits 704 # number of overall hits system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses system.cpu.icache.demand_misses 241 # number of demand (read+write) misses system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8775500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8775500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8775500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 976 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 976 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.246926 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.246926 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.246926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36412.863071 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36412.863071 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 945 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 945 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 945 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.255026 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.255026 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.255026 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -348,52 +347,52 @@ system.cpu.icache.ReadReq_mshr_misses 185 # nu system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6554000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6554000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6554000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.189549 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.189549 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.189549 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35427.027027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.195767 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.195767 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.195767 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.779373 # Cycle average of tags in use -system.cpu.dcache.total_refs 794 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use +system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.341176 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 45.779373 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 572 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.demand_hits 794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 794 # number of overall hits -system.cpu.dcache.ReadReq_misses 116 # number of ReadReq misses +system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 765 # number of overall hits +system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3872000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6688500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6688500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 982 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 982 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.168605 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.191446 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.191446 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33379.310345 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35577.127660 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35577.127660 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,50 +402,50 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 103 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 88 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2169000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3037500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3037500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3041000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.094720 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.086558 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.086558 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35500 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.090618 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.090618 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 121.331762 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 121.331762 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003703 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 120.203882 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003668 # Average percentage of cache occupancy system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 8443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 8447500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9274500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 9278500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9278500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses @@ -455,10 +454,10 @@ system.cpu.l2cache.ReadReq_miss_rate 1 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34323.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34350 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34350 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34364.814815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,19 +474,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 24 # nu system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 7661500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 8415500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 8415500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8417500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8417500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.178862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 357a5d59d..57d02de26 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:43 -gem5 started Jul 8 2011 15:23:20 +gem5 compiled Jul 15 2011 18:02:03 +gem5 started Jul 16 2011 04:26:12 gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 9834500 because target called exit() +Exiting @ tick 9807000 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index d884999d2..6012e4873 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 9834500 # Number of ticks simulated +sim_ticks 9807000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38040 # Simulator instruction rate (inst/s) -host_tick_rate 65174027 # Simulator tick rate (ticks/s) -host_mem_usage 253652 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 35563 # Simulator instruction rate (inst/s) +host_tick_rate 60757564 # Simulator tick rate (ticks/s) +host_mem_usage 253712 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,244 +51,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 19670 # number of cpu cycles simulated +system.cpu.numCycles 19615 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2538 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1884 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2511 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1859 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1886 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 760 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1876 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 752 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6290 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12764 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1028 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2852 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1030 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6264 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12675 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2511 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1020 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2829 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1652 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1029 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2054 # Number of cache lines fetched +system.cpu.fetch.CacheLines 2035 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.423857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.772019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11271 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.423476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.772468 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8482 74.84% 74.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 284 2.51% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 192 1.69% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 2.17% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 242 2.14% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 324 2.86% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 124 1.09% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 120 1.06% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1320 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8442 74.90% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.43% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 191 1.69% 79.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 247 2.19% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 241 2.14% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 319 2.83% 86.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 123 1.09% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 122 1.08% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1312 11.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129029 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.648907 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1079 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2654 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 60 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 11271 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.128014 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.646189 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6547 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1078 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2630 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 955 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14169 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 14078 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6862 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 955 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6833 # Number of cycles rename is idle system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13321 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2402 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 182 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13232 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12898 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 60750 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 59430 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12797 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 60391 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 59071 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7209 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 7108 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2701 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1759 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11506 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 440 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2692 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1760 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11421 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9339 # Number of instructions issued +system.cpu.iq.iqInstsIssued 9287 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 5147 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13929 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.823981 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.484525 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11271 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.823973 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485474 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7613 67.17% 67.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1341 11.83% 79.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 855 7.54% 86.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 564 4.98% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 476 4.20% 95.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 284 2.51% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 1.30% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 42 0.37% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7571 67.17% 67.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1335 11.84% 79.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 851 7.55% 86.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 557 4.94% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 476 4.22% 95.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.47% 98.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 148 1.31% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43 0.38% 99.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11271 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.79% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 64.19% 66.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.75% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 141 64.68% 67.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 32.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5727 61.32% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.07% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2324 24.88% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1278 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5675 61.11% 61.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2324 25.02% 86.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1278 13.76% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9339 # Type of FU issued -system.cpu.iq.rate 0.474784 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023022 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30256 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8361 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9287 # Type of FU issued +system.cpu.iq.rate 0.473464 # Inst issue rate +system.cpu.iq.fu_busy_cnt 218 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023474 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30092 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16563 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8319 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9514 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9465 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1500 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1491 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 955 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11534 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 218 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2701 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1759 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11449 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 210 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2692 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1760 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8897 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 301 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 397 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8853 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2124 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 434 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1479 # Number of branches executed +system.cpu.iew.exec_refs 3346 # number of memory reference insts executed +system.cpu.iew.exec_branches 1462 # Number of branches executed system.cpu.iew.exec_stores 1222 # Number of stores executed -system.cpu.iew.exec_rate 0.452313 # Inst execution rate -system.cpu.iew.wb_sent 8556 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8377 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3980 # num instructions producing a value -system.cpu.iew.wb_consumers 7830 # num instructions consuming a value +system.cpu.iew.exec_rate 0.451338 # Inst execution rate +system.cpu.iew.wb_sent 8511 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8335 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3964 # num instructions producing a value +system.cpu.iew.wb_consumers 7808 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.425877 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508301 # average fanout of values written-back +system.cpu.iew.wb_rate 0.424930 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.507684 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5552 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 351 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10367 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.553583 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.355703 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.556266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.365268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8010 77.26% 77.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1098 10.59% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 4.18% 92.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 284 2.74% 94.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.77% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.62% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.65% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.38% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 84 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7976 77.31% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1088 10.55% 87.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 426 4.13% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 280 2.71% 94.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.77% 96.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 171 1.66% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.65% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 38 0.37% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10317 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed @@ -298,49 +298,49 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21505 # The number of ROB reads -system.cpu.rob.rob_writes 23748 # The number of ROB writes +system.cpu.rob.rob_reads 21363 # The number of ROB reads +system.cpu.rob.rob_writes 23555 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8336 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 8344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.427426 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.427426 # CPI: Total CPI of All Threads -system.cpu.ipc 0.291764 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.291764 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40468 # number of integer regfile reads -system.cpu.int_regfile_writes 8226 # number of integer regfile writes +system.cpu.cpi 3.417843 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.417843 # CPI: Total CPI of All Threads +system.cpu.ipc 0.292582 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.292582 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40304 # number of integer regfile reads +system.cpu.int_regfile_writes 8184 # number of integer regfile writes system.cpu.fp_regfile_reads 29 # number of floating regfile reads -system.cpu.misc_regfile_reads 15801 # number of misc regfile reads +system.cpu.misc_regfile_reads 15709 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 150.859133 # Cycle average of tags in use -system.cpu.icache.total_refs 1688 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 150.950866 # Cycle average of tags in use +system.cpu.icache.total_refs 1669 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.702703 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.638514 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 150.859133 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.073662 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1688 # number of ReadReq hits -system.cpu.icache.demand_hits 1688 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1688 # number of overall hits +system.cpu.icache.occ_blocks::0 150.950866 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.073706 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1669 # number of ReadReq hits +system.cpu.icache.demand_hits 1669 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1669 # number of overall hits system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses system.cpu.icache.demand_misses 366 # number of demand (read+write) misses system.cpu.icache.overall_misses 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12656500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12656500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12656500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.178189 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.178189 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.178189 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34580.601093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34580.601093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34580.601093 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 12661500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12661500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12661500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2035 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2035 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2035 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.179853 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.179853 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.179853 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34594.262295 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34594.262295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34594.262295 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,60 +357,60 @@ system.cpu.icache.ReadReq_mshr_misses 296 # nu system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9940500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9940500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9940500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9939500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9939500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9939500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.144109 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.144109 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.144109 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33582.770270 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.145455 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.145455 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.145455 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33579.391892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33579.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33579.391892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.281770 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 92.326406 # Cycle average of tags in use system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.512821 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.281770 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022530 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 92.326406 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022541 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1791 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits 2400 # number of demand (read+write) hits system.cpu.dcache.overall_hits 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses 178 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses 177 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5526000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 481 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5493000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 16231500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16231500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 16198500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16198500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1968 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2882 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2882 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.090401 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2881 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2881 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.089939 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.167245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31044.943820 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.166956 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.166956 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31033.898305 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33675.311203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33675.311203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33676.715177 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33676.715177 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,41 +420,41 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 326 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 325 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3236000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4741000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4741000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.057897 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.054129 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.054129 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.054148 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.054148 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28385.964912 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30391.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30391.025641 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 190.940380 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 191.048860 # Cycle average of tags in use system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 190.940380 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005827 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 191.048860 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005830 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 43 # number of overall hits @@ -462,10 +462,10 @@ system.cpu.l2cache.ReadReq_misses 367 # nu system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12612500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12610500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14063000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14063000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 14061000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14061000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses @@ -474,10 +474,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.895122 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34366.485014 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34361.035422 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34383.863081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34383.863081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34378.973105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34378.973105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index d2612b5d7..cfd15d7a7 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:04:50 -gem5 started Jul 8 2011 15:22:25 +gem5 compiled Jul 15 2011 17:48:05 +gem5 started Jul 15 2011 20:13:48 gem5 executing on u200439-lin.austin.arm.com command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12285500 because target called exit() +Exiting @ tick 12273500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 39498f791..d9d305c59 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12285500 # Number of ticks simulated +sim_ticks 12273500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28817 # Simulator instruction rate (inst/s) -host_tick_rate 68479139 # Simulator tick rate (ticks/s) -host_mem_usage 244744 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 33014 # Simulator instruction rate (inst/s) +host_tick_rate 78373339 # Simulator tick rate (ticks/s) +host_mem_usage 244788 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,199 +27,199 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24572 # number of cpu cycles simulated +system.cpu.numCycles 24548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1982 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1348 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 1977 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1345 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1584 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 496 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1580 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7946 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12305 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1982 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3034 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1194 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7914 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12271 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1977 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1189 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1787 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.971422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277830 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1783 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.972114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.277844 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9633 76.05% 76.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1253 9.89% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 111 0.88% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 138 1.09% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 289 2.28% 90.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 132 1.04% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 144 1.14% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 875 6.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9597 76.03% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1250 9.90% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 93 0.74% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 870 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080661 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.500773 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8135 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 12623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080536 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.499878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8103 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2867 # Number of cycles decode is running +system.cpu.decode.RunCycles 2859 # Number of cycles decode is running system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 743 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 739 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11438 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 743 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8306 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 739 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8274 # Number of cycles rename is idle system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2750 # Number of cycles rename is running +system.cpu.rename.RunCycles 2742 # Number of cycles rename is running system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11058 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13185 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13180 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3320 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 18 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2359 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2349 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8691 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8651 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7857 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3019 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7822 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1815 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12667 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.620273 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285525 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.619663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.285161 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9298 73.40% 73.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1326 10.47% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 831 6.56% 90.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 513 4.05% 94.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 361 2.85% 97.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 205 1.62% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.67% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.26% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9267 73.41% 73.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1321 10.47% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 831 6.58% 90.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 511 4.05% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.83% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 203 1.61% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 83 0.66% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12667 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12623 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 2.07% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 90 62.07% 64.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 35.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4616 58.75% 58.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2141 27.25% 86.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1092 13.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4598 58.78% 58.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2131 27.24% 86.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1085 13.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7857 # Type of FU issued -system.cpu.iq.rate 0.319754 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018455 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28573 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11730 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7154 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7822 # Type of FU issued +system.cpu.iq.rate 0.318641 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018665 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28459 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11666 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7121 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8000 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 7966 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1195 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1185 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 743 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 739 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10089 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10044 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2359 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2349 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -227,44 +227,44 @@ system.cpu.iew.memOrderViolationEvents 9 # Nu system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7573 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2041 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7537 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2031 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1385 # number of nop insts executed -system.cpu.iew.exec_refs 3109 # number of memory reference insts executed -system.cpu.iew.exec_branches 1276 # Number of branches executed -system.cpu.iew.exec_stores 1068 # Number of stores executed -system.cpu.iew.exec_rate 0.308196 # Inst execution rate -system.cpu.iew.wb_sent 7250 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7156 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2771 # num instructions producing a value -system.cpu.iew.wb_consumers 3964 # num instructions consuming a value +system.cpu.iew.exec_nop 1380 # number of nop insts executed +system.cpu.iew.exec_refs 3091 # number of memory reference insts executed +system.cpu.iew.exec_branches 1271 # Number of branches executed +system.cpu.iew.exec_stores 1060 # Number of stores executed +system.cpu.iew.exec_rate 0.307031 # Inst execution rate +system.cpu.iew.wb_sent 7215 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7123 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2761 # num instructions producing a value +system.cpu.iew.wb_consumers 3949 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.291226 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699041 # average fanout of values written-back +system.cpu.iew.wb_rate 0.290166 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699164 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4255 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4210 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.488594 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.274116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.490239 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.276602 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9523 79.86% 79.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 968 8.12% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.50% 93.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 322 2.70% 96.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 146 1.22% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9485 79.81% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 966 8.13% 87.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 656 5.52% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.35% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11884 # Number of insts commited each cycle system.cpu.commit.count 5826 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed @@ -274,49 +274,49 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21891 # The number of ROB reads -system.cpu.rob.rob_writes 20916 # The number of ROB writes +system.cpu.rob.rob_reads 21805 # The number of ROB reads +system.cpu.rob.rob_writes 20822 # The number of ROB writes system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11905 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11925 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.753724 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.753724 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210361 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210361 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10347 # number of integer regfile reads -system.cpu.int_regfile_writes 5013 # number of integer regfile writes +system.cpu.cpi 4.749081 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.749081 # CPI: Total CPI of All Threads +system.cpu.ipc 0.210567 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210567 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10287 # number of integer regfile reads +system.cpu.int_regfile_writes 4991 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 154 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.262110 # Cycle average of tags in use -system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use +system.cpu.icache.total_refs 1364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.068452 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.059524 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 161.262110 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078741 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits -system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1367 # number of overall hits -system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.icache.demand_misses 420 # number of demand (read+write) misses -system.cpu.icache.overall_misses 420 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15216000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15216000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15216000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1787 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1787 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1787 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.235031 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.235031 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.235031 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36228.571429 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36228.571429 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36228.571429 # average overall miss latency +system.cpu.icache.occ_blocks::0 161.223747 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1364 # number of ReadReq hits +system.cpu.icache.demand_hits 1364 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1364 # number of overall hits +system.cpu.icache.ReadReq_misses 419 # number of ReadReq misses +system.cpu.icache.demand_misses 419 # number of demand (read+write) misses +system.cpu.icache.overall_misses 419 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15179500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15179500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15179500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1783 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1783 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1783 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.234997 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.234997 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.234997 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36227.923628 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36227.923628 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36227.923628 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,59 +326,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 84 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 84 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 84 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11782000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11782000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11782000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.188025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.188025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.188025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35065.476190 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.188446 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.188446 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.188446 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.136669 # Cycle average of tags in use -system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.122056 # Cycle average of tags in use +system.cpu.dcache.total_refs 2382 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.838028 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.774648 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.136669 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022494 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1813 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 92.122056 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1804 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits -system.cpu.dcache.demand_hits 2391 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2391 # number of overall hits -system.cpu.dcache.ReadReq_misses 135 # number of ReadReq misses +system.cpu.dcache.demand_hits 2382 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2382 # number of overall hits +system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses -system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4832000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11507500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16339500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16339500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 481 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4801000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11505500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 16306500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16306500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1938 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2873 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2873 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.069302 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.069143 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.167769 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167769 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35792.592593 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33162.824207 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33899.377593 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33899.377593 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.168006 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.168006 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35828.358209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33157.060519 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33901.247401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33901.247401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,40 +388,40 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 340 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 340 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 339 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1836500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5108500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5108500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1835500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5107500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5107500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.046715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.046956 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.049426 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.049426 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.049598 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.049598 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36009.803922 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35990.196078 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.568003 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.520650 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.568003 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.520650 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 3 # number of overall hits @@ -429,10 +429,10 @@ system.cpu.l2cache.ReadReq_misses 424 # nu system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1761000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16322000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14561500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1760000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16321500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16321500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses @@ -441,10 +441,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.992974 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34529.411765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34362.105263 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34362.105263 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34343.160377 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34509.803922 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34361.052632 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34361.052632 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,19 +461,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 51 # nu system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13198500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1599500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14798000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14798000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.537736 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31362.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 3b8650bce..d1cb3e246 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:06:16 -gem5 started Jul 8 2011 15:22:37 +gem5 compiled Jul 15 2011 17:49:29 +gem5 started Jul 15 2011 20:14:11 gem5 executing on u200439-lin.austin.arm.com command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11010500 because target called exit() +Exiting @ tick 10910500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index d012d707f..bac6ac3e3 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11010500 # Number of ticks simulated +sim_ticks 10910500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36368 # Simulator instruction rate (inst/s) -host_tick_rate 69032646 # Simulator tick rate (ticks/s) -host_mem_usage 241332 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 31106 # Simulator instruction rate (inst/s) +host_tick_rate 58503850 # Simulator tick rate (ticks/s) +host_mem_usage 241340 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,244 +27,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22022 # number of cpu cycles simulated +system.cpu.numCycles 21822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2367 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1975 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2297 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1905 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1913 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 666 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6529 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13348 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2367 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 869 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2278 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1276 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 941 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 6507 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2297 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 855 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1212 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 909 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1754 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 10610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.258058 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.653017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 10433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.243746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.642546 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8332 78.53% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 151 1.42% 79.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.74% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 141 1.33% 83.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 226 2.13% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 137 1.29% 86.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 2.67% 89.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 123 1.16% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1032 9.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8223 78.82% 78.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 152 1.46% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 173 1.66% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 127 1.22% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 217 2.08% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 137 1.31% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 283 2.71% 89.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 122 1.17% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 999 9.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 10610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107483 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6699 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1011 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2107 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 711 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 10433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.105261 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.594629 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6670 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 983 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2045 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 656 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11818 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11459 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 711 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6902 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6866 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 379 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1977 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 278 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11283 # Number of instructions processed by rename +system.cpu.rename.RunCycles 1920 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 262 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 10928 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9842 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18439 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18368 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 207 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9549 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17781 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4835 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4542 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 566 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1897 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1627 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.rename.skidInsts 544 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1864 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1573 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9933 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8750 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8536 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4202 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3878 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3544 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 10610 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.824694 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 10433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.818173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.531685 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7338 69.16% 69.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1037 9.77% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 771 7.27% 86.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 497 4.68% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 4.31% 95.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 303 2.86% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.27% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.46% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7234 69.34% 69.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1021 9.79% 79.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 7.30% 86.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 472 4.52% 90.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 448 4.29% 95.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 290 2.78% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 132 1.27% 99.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 51 0.49% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 10610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 10433 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 6.45% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 68 43.87% 50.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 49.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.84% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 68 44.16% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5520 63.09% 63.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1751 20.01% 83.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1477 16.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5388 63.12% 63.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1717 20.11% 83.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1429 16.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8750 # Type of FU issued -system.cpu.iq.rate 0.397330 # Inst issue rate -system.cpu.iq.fu_busy_cnt 155 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017714 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28255 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14489 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8536 # Type of FU issued +system.cpu.iq.rate 0.391165 # Inst issue rate +system.cpu.iq.fu_busy_cnt 154 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018041 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 27649 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13831 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7849 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8867 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8652 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 935 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 902 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 581 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 527 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 711 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 656 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10327 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10002 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1897 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1627 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1864 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1573 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 239 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 301 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8358 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1644 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 392 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 238 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 300 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8170 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3035 # number of memory reference insts executed -system.cpu.iew.exec_branches 1315 # Number of branches executed -system.cpu.iew.exec_stores 1391 # Number of stores executed -system.cpu.iew.exec_rate 0.379530 # Inst execution rate -system.cpu.iew.wb_sent 8174 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4233 # num instructions producing a value -system.cpu.iew.wb_consumers 6765 # num instructions consuming a value +system.cpu.iew.exec_refs 2952 # number of memory reference insts executed +system.cpu.iew.exec_branches 1313 # Number of branches executed +system.cpu.iew.exec_stores 1341 # Number of stores executed +system.cpu.iew.exec_rate 0.374393 # Inst execution rate +system.cpu.iew.wb_sent 7993 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7879 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4173 # num instructions producing a value +system.cpu.iew.wb_consumers 6691 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.365907 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.625721 # average fanout of values written-back +system.cpu.iew.wb_rate 0.361058 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 9899 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.585918 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.365203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 9777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.593229 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.375317 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7502 75.79% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 985 9.95% 85.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 645 6.52% 92.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.65% 94.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 188 1.90% 96.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 118 1.19% 97.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 77 0.78% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.41% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 81 0.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7386 75.54% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 981 10.03% 85.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 642 6.57% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.68% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 190 1.94% 96.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 116 1.19% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 75 0.77% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.42% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 84 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 9899 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle system.cpu.commit.count 5800 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2008 # Number of memory references committed @@ -274,45 +274,45 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 81 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 20151 # The number of ROB reads -system.cpu.rob.rob_writes 21378 # The number of ROB writes -system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11412 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 19701 # The number of ROB reads +system.cpu.rob.rob_writes 20673 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.796897 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.796897 # CPI: Total CPI of All Threads -system.cpu.ipc 0.263373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.263373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13256 # number of integer regfile reads -system.cpu.int_regfile_writes 7085 # number of integer regfile writes +system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads +system.cpu.ipc 0.265787 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265787 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12979 # number of integer regfile reads +system.cpu.int_regfile_writes 6957 # number of integer regfile writes system.cpu.fp_regfile_reads 28 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 169.489368 # Cycle average of tags in use -system.cpu.icache.total_refs 1334 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 169.539680 # Cycle average of tags in use +system.cpu.icache.total_refs 1291 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.800570 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 169.489368 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.082758 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1334 # number of ReadReq hits -system.cpu.icache.demand_hits 1334 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1334 # number of overall hits +system.cpu.icache.occ_blocks::0 169.539680 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.082783 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1291 # number of ReadReq hits +system.cpu.icache.demand_hits 1291 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1291 # number of overall hits system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses system.cpu.icache.demand_misses 420 # number of demand (read+write) misses system.cpu.icache.overall_misses 420 # number of overall misses system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.239453 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.239453 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.239453 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.245470 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.245470 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.245470 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency @@ -336,9 +336,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.200114 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.200114 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.200114 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.205143 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.205143 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.205143 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency @@ -347,37 +347,37 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 66.389041 # Cycle average of tags in use -system.cpu.dcache.total_refs 2180 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 66.296919 # Cycle average of tags in use +system.cpu.dcache.total_refs 2156 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 20.761905 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.533333 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 66.389041 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.016208 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 735 # number of WriteReq hits -system.cpu.dcache.demand_hits 2180 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2180 # number of overall hits -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu.dcache.demand_misses 401 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 401 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10558500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13569500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13569500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 66.296919 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.016186 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1428 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 728 # number of WriteReq hits +system.cpu.dcache.demand_hits 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 318 # number of WriteReq misses +system.cpu.dcache.demand_misses 406 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2947000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10802500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 13749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 13749500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2581 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.058632 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.297323 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.155366 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.155366 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33455.555556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33950.160772 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33839.152120 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33839.152120 # average overall miss latency +system.cpu.dcache.demand_accesses 2562 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.058047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.304015 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.158470 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.158470 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33488.636364 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33970.125786 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33865.763547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33865.763547 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,39 +387,39 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 296 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 57 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 105 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 105 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3714000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3714000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1751000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3714500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.037134 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.040682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.040682 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.040984 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.040984 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34447.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35376.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35376.190476 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.598447 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 200.613051 # Cycle average of tags in use system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 200.598447 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 200.613051 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.006122 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 9 # number of ReadReq hits system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits @@ -429,9 +429,9 @@ system.cpu.l2cache.ReadExReq_misses 48 # nu system.cpu.l2cache.demand_misses 447 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 447 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 13714000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1678000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 15392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 15392000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1678500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15392500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15392500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 456 # number of demand (read+write) accesses @@ -441,9 +441,9 @@ system.cpu.l2cache.ReadExReq_miss_rate 1 # mi system.cpu.l2cache.demand_miss_rate 0.980263 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.980263 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34958.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34434.004474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34434.004474 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34968.750000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34435.123043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34435.123043 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,19 +460,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 48 # nu system.cpu.l2cache.demand_mshr_misses 447 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 447 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12434000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13959500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13959500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13960000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977941 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.980263 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.980263 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.654135 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index e361952bb..66b7170d9 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:15 -gem5 started Jul 8 2011 15:23:04 +gem5 compiled Jul 15 2011 18:01:24 +gem5 started Jul 16 2011 00:22:08 gem5 executing on u200439-lin.austin.arm.com command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11102000 because target called exit() +Exiting @ tick 11087000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index a1f123e22..f6f7897f3 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11102000 # Number of ticks simulated +sim_ticks 11087000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58378 # Simulator instruction rate (inst/s) -host_tick_rate 66066423 # Simulator tick rate (ticks/s) -host_mem_usage 248304 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 48237 # Simulator instruction rate (inst/s) +host_tick_rate 54512378 # Simulator tick rate (ticks/s) +host_mem_usage 248340 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 22205 # number of cpu cycles simulated +system.cpu.numCycles 22175 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3070 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3070 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 3057 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3057 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2745 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 1002 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2732 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 5900 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14062 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3070 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2234 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 5894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14000 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3057 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2223 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1500 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.933552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.219407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1891 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.930776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.218766 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9243 70.43% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 169 1.29% 71.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.34% 73.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 241 1.84% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 234 1.78% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 195 1.49% 78.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 280 2.13% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.07% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2444 18.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9227 70.50% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 167 1.28% 71.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 175 1.34% 73.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 239 1.83% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 232 1.77% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 193 1.47% 78.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 279 2.13% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 139 1.06% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2437 18.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.138257 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.633281 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6251 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1454 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3582 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 112 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1724 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24194 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1724 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6540 # Number of cycles rename is idle +system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137858 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.631342 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3564 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1713 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24084 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1713 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6535 # Number of cycles rename is idle system.cpu.rename.BlockCycles 523 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 524 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3382 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 430 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22801 # Number of instructions processed by rename +system.cpu.rename.RunCycles 3364 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 429 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 271 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21341 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47863 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47847 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 21249 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 47660 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 47644 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11973 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 11881 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1611 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2253 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1786 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1609 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2239 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1783 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20643 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17013 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13151 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13123 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.296426 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.004622 # Number of insts issued each cycle +system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20542 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 16959 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13000 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.295767 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.003323 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8026 61.16% 61.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1107 8.44% 69.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1007 7.67% 77.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 730 5.56% 82.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 676 5.15% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 728 5.55% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 620 4.72% 98.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 194 1.48% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 35 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1107 8.46% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1007 7.69% 77.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 196 1.50% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 34 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13088 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 95 66.90% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 16.90% 83.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 16.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 94 66.67% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24 17.02% 83.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13681 80.41% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1854 10.90% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1474 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1844 10.87% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17013 # Type of FU issued -system.cpu.iq.rate 0.766179 # Inst issue rate -system.cpu.iq.fu_busy_cnt 142 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008347 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 47348 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30994 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15803 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 16959 # Type of FU issued +system.cpu.iq.rate 0.764780 # Inst issue rate +system.cpu.iq.fu_busy_cnt 141 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008314 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 47202 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30805 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15753 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17147 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17092 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1197 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1183 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 852 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1713 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 15 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2253 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1786 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2239 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1783 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16148 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1748 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 865 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 523 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16098 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 861 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3114 # number of memory reference insts executed -system.cpu.iew.exec_branches 1606 # Number of branches executed -system.cpu.iew.exec_stores 1366 # Number of stores executed -system.cpu.iew.exec_rate 0.727224 # Inst execution rate -system.cpu.iew.wb_sent 15964 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15807 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10570 # num instructions producing a value -system.cpu.iew.wb_consumers 15744 # num instructions consuming a value +system.cpu.iew.exec_refs 3105 # number of memory reference insts executed +system.cpu.iew.exec_branches 1601 # Number of branches executed +system.cpu.iew.exec_stores 1363 # Number of stores executed +system.cpu.iew.exec_rate 0.725953 # Inst execution rate +system.cpu.iew.wb_sent 15916 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15757 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10536 # num instructions producing a value +system.cpu.iew.wb_consumers 15696 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.711867 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.671367 # average fanout of values written-back +system.cpu.iew.wb_rate 0.710575 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.671254 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 10868 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10766 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 497 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11399 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.860514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.681683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.862330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.686905 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7958 69.81% 69.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1091 9.57% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 577 5.06% 84.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 889 7.80% 92.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 346 3.04% 95.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 149 1.31% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 139 1.22% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 66 0.58% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 184 1.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7943 69.83% 69.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1088 9.56% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 574 5.05% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 883 7.76% 92.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 343 3.02% 95.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 152 1.34% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 139 1.22% 97.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.58% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 187 1.64% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11375 # Number of insts commited each cycle system.cpu.commit.count 9809 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 187 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 31892 # The number of ROB reads -system.cpu.rob.rob_writes 43113 # The number of ROB writes +system.cpu.rob.rob_reads 31763 # The number of ROB reads +system.cpu.rob.rob_writes 42898 # The number of ROB writes system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9082 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 9087 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.263737 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.263737 # CPI: Total CPI of All Threads -system.cpu.ipc 0.441747 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.441747 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23720 # number of integer regfile reads -system.cpu.int_regfile_writes 14686 # number of integer regfile writes +system.cpu.cpi 2.260679 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.260679 # CPI: Total CPI of All Threads +system.cpu.ipc 0.442345 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.442345 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23665 # number of integer regfile reads +system.cpu.int_regfile_writes 14643 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7234 # number of misc regfile reads +system.cpu.misc_regfile_reads 7210 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.121253 # Cycle average of tags in use -system.cpu.icache.total_refs 1536 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 145.144237 # Cycle average of tags in use +system.cpu.icache.total_refs 1527 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.154362 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.124161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 145.121253 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.070860 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1536 # number of ReadReq hits -system.cpu.icache.demand_hits 1536 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1536 # number of overall hits +system.cpu.icache.occ_blocks::0 145.144237 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.070871 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1527 # number of ReadReq hits +system.cpu.icache.demand_hits 1527 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1527 # number of overall hits system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses system.cpu.icache.demand_misses 364 # number of demand (read+write) misses system.cpu.icache.overall_misses 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13311000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13311000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13311000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1900 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.191579 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.191579 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.191579 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36568.681319 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36568.681319 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36568.681319 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 13314500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 13314500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 13314500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1891 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1891 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1891 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.192491 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.192491 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.192491 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36578.296703 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36578.296703 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36578.296703 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -313,52 +313,52 @@ system.cpu.icache.ReadReq_mshr_misses 298 # nu system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10465000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10465000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10465000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10466500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10466500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10466500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.156842 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.156842 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.156842 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35117.449664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.157589 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.157589 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.157589 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35122.483221 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.500276 # Cycle average of tags in use -system.cpu.dcache.total_refs 2118 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.499149 # Cycle average of tags in use +system.cpu.dcache.total_refs 2112 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.606897 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.565517 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 85.500276 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 85.499149 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.020874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1500 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1494 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 618 # number of WriteReq hits -system.cpu.dcache.demand_hits 2118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2118 # number of overall hits +system.cpu.dcache.demand_hits 2112 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2112 # number of overall hits system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 316 # number of WriteReq misses system.cpu.dcache.demand_misses 429 # number of demand (read+write) misses system.cpu.dcache.overall_misses 429 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 3938500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10704500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 14643000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 14643000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency 10708500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 14647000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 14647000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1607 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2547 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2547 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.070056 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2541 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2541 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.070317 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.338330 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.168433 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.168433 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate 0.168831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.168831 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33875 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34132.867133 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34132.867133 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33887.658228 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34142.191142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34142.191142 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,17 +377,17 @@ system.cpu.dcache.WriteReq_mshr_misses 77 # nu system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2421500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2762000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2422500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2761000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 5183500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 5183500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.042777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.042937 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.057322 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.057322 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35094.202899 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35870.129870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.057458 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.057458 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35108.695652 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35857.142857 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency @@ -395,13 +395,13 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.583785 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.614114 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005495 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 178.583785 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005450 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.614114 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005451 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits @@ -409,10 +409,10 @@ system.cpu.l2cache.ReadReq_misses 365 # nu system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12493000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2653500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 15146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 15146500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12494500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2654000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15148500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15148500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 367 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses @@ -421,10 +421,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.994550 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34227.397260 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.038961 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34268.099548 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34268.099548 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34231.506849 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34467.532468 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34272.624434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34272.624434 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -441,19 +441,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 77 # nu system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11330000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 2409500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13737500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13739500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13739500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994550 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.616438 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.095890 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |