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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-08 18:07:54 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-08 18:07:54 -0800
commit4eab18fd063fe80203751b6b058ea232e402d879 (patch)
treec6a57820ea7aeb7da4f1d66776720f9c2ae7f7d3 /tests/quick/00.hello
parentea9d4c3a97b1570a3b30d2fd538514b53ac54944 (diff)
downloadgem5-4eab18fd063fe80203751b6b058ea232e402d879.tar.xz
regess: protocol regression tester updates
Diffstat (limited to 'tests/quick/00.hello')
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini14
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats28
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt26
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini68
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats54
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt26
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini68
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats92
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt24
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini95
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats164
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt30
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini14
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats26
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt26
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini68
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats54
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt26
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini68
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats60
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt24
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini97
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats164
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt30
32 files changed, 805 insertions, 609 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index 2d9b77211..c905c3ec3 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -186,6 +195,7 @@ tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
+access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 1eb50eecd..50b357793 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/13/2011 22:36:30
+Real time: Feb/08/2011 17:31:55
Profiler Stats
--------------
-Elapsed_time_in_seconds: 2
-Elapsed_time_in_minutes: 0.0333333
-Elapsed_time_in_hours: 0.000555556
-Elapsed_time_in_days: 2.31481e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 1.2
-Virtual_time_in_minutes: 0.02
-Virtual_time_in_hours: 0.000333333
-Virtual_time_in_days: 1.38889e-05
+Virtual_time_in_seconds: 0.51
+Virtual_time_in_minutes: 0.0085
+Virtual_time_in_hours: 0.000141667
+Virtual_time_in_days: 5.90278e-06
Ruby_current_time: 275313
Ruby_start_time: 0
Ruby_cycles: 275313
-mbytes_resident: 22.0195
-mbytes_total: 156.82
-resident_ratio: 0.140462
+mbytes_resident: 37.0469
+mbytes_total: 210.465
+resident_ratio: 0.176098
ruby_cycles_executed: [ 275314 ]
@@ -117,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standa
Resource Usage
--------------
page_size: 4096
-user_time: 1
+user_time: 0
system_time: 0
-page_reclaims: 6300
+page_reclaims: 10681
page_faults: 0
swaps: 0
block_inputs: 0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 4d60ccfef..8e7f8bf86 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 13 2011 22:36:25
-M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
-M5 started Jan 13 2011 22:36:28
-M5 executing on scamorza.cs.wisc.edu
+M5 compiled Feb 8 2011 17:31:51
+M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:31:55
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index be34966e1..d0f6b1167 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 4080 # Simulator instruction rate (inst/s)
-host_mem_usage 160588 # Number of bytes of host memory used
-host_seconds 1.57 # Real time elapsed on the host
-host_tick_rate 175338 # Simulator tick rate (ticks/s)
+host_inst_rate 30108 # Simulator instruction rate (inst/s)
+host_mem_usage 215520 # Number of bytes of host memory used
+host_seconds 0.21 # Real time elapsed on the host
+host_tick_rate 1293296 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000275 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 275313 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 275313 # Number of busy cycles
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_fp_insts 10 # number of float instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_refs 2060 # Number of memory references
+system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
+system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 756bebd28..cb765942a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -108,32 +117,19 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
-L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+children=L1DcacheMemory L1IcacheMemory
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
-[system.l1_cntrl0.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.l1_cntrl0.sequencer.dcache
-deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.l1_cntrl0.sequencer.dcache]
+[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=3
@@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.sequencer.icache]
+[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=3
@@ -177,14 +173,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
-debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@@ -194,13 +189,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -216,9 +216,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
-name=Crossbar
num_int_nodes=4
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index c3c1c36bf..9154f09df 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: Crossbar
+topology:
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Aug/05/2010 10:35:39
+Real time: Feb/08/2011 17:41:43
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.44
-Virtual_time_in_minutes: 0.00733333
-Virtual_time_in_hours: 0.000122222
-Virtual_time_in_days: 5.09259e-06
+Virtual_time_in_seconds: 0.52
+Virtual_time_in_minutes: 0.00866667
+Virtual_time_in_hours: 0.000144444
+Virtual_time_in_days: 6.01852e-06
Ruby_current_time: 223854
Ruby_start_time: 0
Ruby_cycles: 223854
-mbytes_resident: 34.9609
-mbytes_total: 34.9688
-resident_ratio: 1
+mbytes_resident: 37.1562
+mbytes_total: 210.609
+resident_ratio: 0.176478
ruby_cycles_executed: [ 223855 ]
@@ -119,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7630
-page_faults: 2184
+page_reclaims: 10696
+page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.349752
outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.sequencer.icache
- system.l1_cntrl0.sequencer.icache_total_misses: 0
- system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
- system.l1_cntrl0.sequencer.icache_total_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+ system.l1_cntrl0.L1IcacheMemory_total_misses: 0
+ system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
-Cache Stats: system.l1_cntrl0.sequencer.dcache
- system.l1_cntrl0.sequencer.dcache_total_misses: 0
- system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
- system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+ system.l1_cntrl0.L1DcacheMemory_total_misses: 0
+ system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
--- L1Cache ---
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index 7e21d792f..c4db03463 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 5 2010 10:34:54
-M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
-M5 started Aug 5 2010 10:35:39
-M5 executing on svvint09
+M5 compiled Feb 8 2011 17:41:34
+M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:41:42
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index add084384..e92c6159b 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 23717 # Simulator instruction rate (inst/s)
-host_mem_usage 212528 # Number of bytes of host memory used
-host_seconds 0.27 # Real time elapsed on the host
-host_tick_rate 829037 # Simulator tick rate (ticks/s)
+host_inst_rate 26297 # Simulator instruction rate (inst/s)
+host_mem_usage 215668 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
+host_tick_rate 918519 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000224 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 223854 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 223854 # Number of busy cycles
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_fp_insts 10 # number of float instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_refs 2060 # Number of memory references
+system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
+system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index d5555ef31..d946bdc6f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,9 +120,9 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
-L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+children=L1DcacheMemory L1IcacheMemory
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
buffer_size=0
dynamic_timeout_enabled=true
@@ -125,24 +134,11 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
-[system.l1_cntrl0.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.l1_cntrl0.sequencer.dcache
-deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.l1_cntrl0.sequencer.dcache]
+[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=2
@@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.sequencer.icache]
+[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=2
@@ -188,14 +184,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
-debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@@ -205,13 +200,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -227,9 +227,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
-name=Crossbar
num_int_nodes=4
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 39236835d..223551577 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: Crossbar
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Aug/05/2010 10:42:35
+Real time: Feb/08/2011 17:51:05
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.27
-Virtual_time_in_minutes: 0.0045
-Virtual_time_in_hours: 7.5e-05
-Virtual_time_in_days: 3.125e-06
+Virtual_time_in_seconds: 0.4
+Virtual_time_in_minutes: 0.00666667
+Virtual_time_in_hours: 0.000111111
+Virtual_time_in_days: 4.62963e-06
Ruby_current_time: 243131
Ruby_start_time: 0
Ruby_cycles: 243131
-mbytes_resident: 34.8711
-mbytes_total: 34.8789
-resident_ratio: 1
+mbytes_resident: 37.0508
+mbytes_total: 210.492
+resident_ratio: 0.176057
ruby_cycles_executed: [ 243132 ]
@@ -70,13 +70,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 277 count: 8464 average: 27.7253 | standard deviation: 60.1519 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 205 count: 6414 average: 18.3709 | standard deviation: 49.3264 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 277 count: 1185 average: 71.3747 | standard deviation: 82.6759 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.2913 | standard deviation: 68.2683 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ]
miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ]
-miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 2 max: 277 count: 1301 average: 168.209 | standard deviation: 13.9628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -89,13 +89,13 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 ave
imcomplete_dir_Times: 1300
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 205 count: 636 average: 166.8 | standard deviation: 8.47154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ]
-miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 2 max: 277 count: 487 average: 169.324 | standard deviation: 17.4353 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ]
-miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.191 | standard deviation: 18.0345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -127,8 +127,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7568
-page_faults: 2181
+page_reclaims: 10655
+page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -197,28 +197,28 @@ links_utilized_percent_switch_3: 0.209297
outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.sequencer.icache
- system.l1_cntrl0.sequencer.icache_total_misses: 646
- system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
- system.l1_cntrl0.sequencer.icache_total_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+ system.l1_cntrl0.L1IcacheMemory_total_misses: 646
+ system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
+ system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+ system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
- system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
+ system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 646 100%
-Cache Stats: system.l1_cntrl0.sequencer.dcache
- system.l1_cntrl0.sequencer.dcache_total_misses: 734
- system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734
- system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+ system.l1_cntrl0.L1DcacheMemory_total_misses: 734
+ system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 734
+ system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_request_type_LD: 71.5259%
- system.l1_cntrl0.sequencer.dcache_request_type_ST: 28.4741%
+ system.l1_cntrl0.L1DcacheMemory_request_type_LD: 71.5259%
+ system.l1_cntrl0.L1DcacheMemory_request_type_ST: 28.4741%
- system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 734 100%
+ system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 734 100%
--- L1Cache ---
- Event Counts -
@@ -226,7 +226,7 @@ Load [1185 ] 1185
Ifetch [6414 ] 6414
Store [865 ] 865
Atomic [0 ] 0
-L1_Replacement [1384 ] 1384
+L1_Replacement [1365 ] 1365
Data_Shared [48 ] 48
Data_Owner [0 ] 0
Data_All_Tokens [1332 ] 1332
@@ -356,7 +356,7 @@ M_W Load [102 ] 102
M_W Ifetch [2271 ] 2271
M_W Store [25 ] 25
M_W Atomic [0 ] 0
-M_W L1_Replacement [21 ] 21
+M_W L1_Replacement [8 ] 8
M_W Transient_GETX [0 ] 0
M_W Transient_Local_GETX [0 ] 0
M_W Transient_GETS [0 ] 0
@@ -373,7 +373,7 @@ MM_W Load [21 ] 21
MM_W Ifetch [0 ] 0
MM_W Store [265 ] 265
MM_W Atomic [0 ] 0
-MM_W L1_Replacement [9 ] 9
+MM_W L1_Replacement [3 ] 3
MM_W Transient_GETX [0 ] 0
MM_W Transient_Local_GETX [0 ] 0
MM_W Transient_GETS [0 ] 0
@@ -743,18 +743,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_reads: 1301
memory_writes: 241
memory_refreshes: 507
- memory_total_request_delays: 714
- memory_delays_per_request: 0.463035
+ memory_total_request_delays: 709
+ memory_delays_per_request: 0.459792
memory_delays_in_input_queue: 240
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 474
- memory_stalls_for_bank_busy: 148
+ memory_delays_stalled_at_head_of_bank_queue: 469
+ memory_stalls_for_bank_busy: 141
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 30
- memory_stalls_for_bus: 278
+ memory_stalls_for_arbitration: 33
+ memory_stalls_for_bus: 279
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 18
+ memory_stalls_for_read_write_turnaround: 16
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index bfe534678..0a28f3bb1 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 5 2010 10:41:36
-M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
-M5 started Aug 5 2010 10:42:35
-M5 executing on svvint09
+M5 compiled Feb 8 2011 17:50:56
+M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:51:05
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 4330907be..a8a90f72d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 45740 # Simulator instruction rate (inst/s)
-host_mem_usage 212336 # Number of bytes of host memory used
+host_inst_rate 46789 # Simulator instruction rate (inst/s)
+host_mem_usage 215548 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
-host_tick_rate 1736538 # Simulator tick rate (ticks/s)
+host_tick_rate 1774187 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000243 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 243131 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 243131 # Number of busy cycles
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_fp_insts 10 # number of float instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_refs 2060 # Number of memory references
+system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
+system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index a5602ce6c..b25662a67 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -70,6 +79,7 @@ type=Directory_Controller
children=directory memBuffer probeFilter
buffer_size=0
directory=system.dir_cntrl0.directory
+full_bit_dir_enabled=false
memBuffer=system.dir_cntrl0.memBuffer
memory_controller_latency=2
number_of_TBEs=256
@@ -118,17 +128,18 @@ start_index_bit=6
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L2cacheMemory sequencer
-L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
-L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+children=L2cacheMemory
+L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
+L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
buffer_size=0
cache_response_latency=10
issue_latency=2
+l2_cache_hit_latency=10
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
@@ -140,12 +151,37 @@ replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
-[system.l1_cntrl0.sequencer]
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.cpu_ruby_ports.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=cpu_ruby_ports network profiler tracer
+block_size_bytes=64
+clock=1
+mem_size=134217728
+network=system.ruby.network
+no_mem_vec=false
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache icache
-dcache=system.l1_cntrl0.sequencer.dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
+icache=system.ruby.cpu_ruby_ports.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
@@ -153,7 +189,7 @@ version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
-[system.l1_cntrl0.sequencer.dcache]
+[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=2
@@ -161,7 +197,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.sequencer.icache]
+[system.ruby.cpu_ruby_ports.icache]
type=RubyCache
assoc=2
latency=2
@@ -169,39 +205,6 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
-
-[system.ruby]
-type=RubySystem
-children=debug network profiler tracer
-block_size_bytes=64
-clock=1
-debug=system.ruby.debug
-mem_size=134217728
-network=system.ruby.network
-no_mem_vec=false
-profiler=system.ruby.profiler
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
-
[system.ruby.network]
type=SimpleNetwork
children=topology
@@ -216,9 +219,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-name=Crossbar
num_int_nodes=3
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index 422144bd2..afe766dd7 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: Crossbar
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Aug/05/2010 11:09:30
+Real time: Feb/08/2011 17:57:03
Profiler Stats
--------------
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.61
-Virtual_time_in_minutes: 0.0101667
-Virtual_time_in_hours: 0.000169444
-Virtual_time_in_days: 7.06019e-06
+Virtual_time_in_seconds: 0.42
+Virtual_time_in_minutes: 0.007
+Virtual_time_in_hours: 0.000116667
+Virtual_time_in_days: 4.86111e-06
-Ruby_current_time: 207970
+Ruby_current_time: 208400
Ruby_start_time: 0
-Ruby_cycles: 207970
+Ruby_cycles: 208400
-mbytes_resident: 34.3633
-mbytes_total: 206.125
-resident_ratio: 0.166768
+mbytes_resident: 36.6641
+mbytes_total: 209.902
+resident_ratio: 0.174709
-ruby_cycles_executed: [ 207971 ]
+ruby_cycles_executed: [ 208401 ]
Busy Controller Counts:
L1Cache-0:0
@@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
+miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
-miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
-miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
+miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
+miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 1158
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
-miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
-miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
+miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
-miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
-miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
+miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -126,7 +126,7 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 9927
+page_reclaims: 10608
page_faults: 0
swaps: 0
block_inputs: 0
@@ -144,9 +144,9 @@ total_msgs: 20718 total_bytes: 430512
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.111284
- links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.111054
+ links_utilized_percent_switch_0_link_0: 0.0694218 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.152687 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.111284
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.158256
- links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.157929
+ links_utilized_percent_switch_1_link_0: 0.0381718 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.277687 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
@@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.158256
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.215632
- links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.215187
+ links_utilized_percent_switch_2_link_0: 0.277687 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.152687 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215632
outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.sequencer.icache
- system.l1_cntrl0.sequencer.icache_total_misses: 646
- system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
- system.l1_cntrl0.sequencer.icache_total_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.ruby.cpu_ruby_ports.icache
+ system.ruby.cpu_ruby_ports.icache_total_misses: 646
+ system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646
+ system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
+ system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
+ system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+ system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
- system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
+ system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 646 100%
-Cache Stats: system.l1_cntrl0.sequencer.dcache
- system.l1_cntrl0.sequencer.dcache_total_misses: 716
- system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716
- system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+Cache Stats: system.ruby.cpu_ruby_ports.dcache
+ system.ruby.cpu_ruby_ports.dcache_total_misses: 716
+ system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716
+ system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
+ system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
+ system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_request_type_LD: 73.324%
- system.l1_cntrl0.sequencer.dcache_request_type_ST: 26.676%
+ system.ruby.cpu_ruby_ports.dcache_request_type_LD: 73.324%
+ system.ruby.cpu_ruby_ports.dcache_request_type_ST: 26.676%
- system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 716 100%
+ system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 716 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory
- system.l1_cntrl0.L2cacheMemory_total_misses: 1159
- system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159
+ system.l1_cntrl0.L2cacheMemory_total_misses: 1362
+ system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.L2cacheMemory_request_type_LD: 36.2381%
- system.l1_cntrl0.L2cacheMemory_request_type_ST: 13.6324%
- system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 50.1294%
+ system.l1_cntrl0.L2cacheMemory_request_type_LD: 38.5463%
+ system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235%
+ system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302%
- system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1159 100%
+ system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1362 100%
--- L1Cache ---
- Event Counts -
-Load [1201 ] 1201
-Ifetch [6436 ] 6436
-Store [919 ] 919
+Load [1193 ] 1193
+Ifetch [6425 ] 6425
+Store [892 ] 892
L2_Replacement [1143 ] 1143
L1_to_L2 [1354 ] 1354
Trigger_L2_to_L1D [138 ] 138
@@ -231,6 +231,7 @@ Other_GETX [0 ] 0
Other_GETS [0 ] 0
Merged_GETS [0 ] 0
Other_GETS_No_Mig [0 ] 0
+NC_DMA_GETS [0 ] 0
Invalidate [0 ] 0
Ack [0 ] 0
Shared_Ack [0 ] 0
@@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0
I Other_GETX [0 ] 0
I Other_GETS [0 ] 0
I Other_GETS_No_Mig [0 ] 0
+I NC_DMA_GETS [0 ] 0
I Invalidate [0 ] 0
S Load [0 ] 0
@@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0
S Other_GETX [0 ] 0
S Other_GETS [0 ] 0
S Other_GETS_No_Mig [0 ] 0
+S NC_DMA_GETS [0 ] 0
S Invalidate [0 ] 0
O Load [0 ] 0
@@ -278,6 +281,7 @@ O Other_GETX [0 ] 0
O Other_GETS [0 ] 0
O Merged_GETS [0 ] 0
O Other_GETS_No_Mig [0 ] 0
+O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
M Load [368 ] 368
@@ -291,6 +295,7 @@ M Other_GETX [0 ] 0
M Other_GETS [0 ] 0
M Merged_GETS [0 ] 0
M Other_GETS_No_Mig [0 ] 0
+M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0
MM Load [397 ] 397
@@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0
MM Other_GETS_No_Mig [0 ] 0
+MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0
IM Load [0 ] 0
@@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0
IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0
+IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0
IM Ack [0 ] 0
IM Data [0 ] 0
@@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0
SM Other_GETX [0 ] 0
SM Other_GETS [0 ] 0
SM Other_GETS_No_Mig [0 ] 0
+SM NC_DMA_GETS [0 ] 0
SM Invalidate [0 ] 0
SM Ack [0 ] 0
SM Data [0 ] 0
+SM Exclusive_Data [0 ] 0
OM Load [0 ] 0
OM Ifetch [0 ] 0
@@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0
OM Other_GETS [0 ] 0
OM Merged_GETS [0 ] 0
OM Other_GETS_No_Mig [0 ] 0
+OM NC_DMA_GETS [0 ] 0
OM Invalidate [0 ] 0
OM Ack [0 ] 0
OM All_acks [0 ] 0
@@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0
IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0
+IS NC_DMA_GETS [0 ] 0
IS Invalidate [0 ] 0
IS Ack [0 ] 0
IS Shared_Ack [0 ] 0
@@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0
OI Other_GETS [0 ] 0
OI Merged_GETS [0 ] 0
OI Other_GETS_No_Mig [0 ] 0
+OI NC_DMA_GETS [0 ] 0
OI Invalidate [0 ] 0
OI Writeback_Ack [0 ] 0
-MI Load [16 ] 16
-MI Ifetch [22 ] 22
-MI Store [54 ] 54
+MI Load [8 ] 8
+MI Ifetch [11 ] 11
+MI Store [27 ] 27
MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0
MI Other_GETS [0 ] 0
MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0
+MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0
MI Writeback_Ack [1143 ] 1143
@@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0
II Other_GETX [0 ] 0
II Other_GETS [0 ] 0
II Other_GETS_No_Mig [0 ] 0
+II NC_DMA_GETS [0 ] 0
II Invalidate [0 ] 0
II Writeback_Ack [0 ] 0
II Writeback_Nack [0 ] 0
@@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0
IT Other_GETS [0 ] 0
IT Merged_GETS [0 ] 0
IT Other_GETS_No_Mig [0 ] 0
+IT NC_DMA_GETS [0 ] 0
IT Invalidate [0 ] 0
ST Load [0 ] 0
@@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0
ST Other_GETS [0 ] 0
ST Merged_GETS [0 ] 0
ST Other_GETS_No_Mig [0 ] 0
+ST NC_DMA_GETS [0 ] 0
ST Invalidate [0 ] 0
OT Load [0 ] 0
@@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0
OT Other_GETS [0 ] 0
OT Merged_GETS [0 ] 0
OT Other_GETS_No_Mig [0 ] 0
+OT NC_DMA_GETS [0 ] 0
OT Invalidate [0 ] 0
MT Load [0 ] 0
@@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0
MT Other_GETS [0 ] 0
MT Merged_GETS [0 ] 0
MT Other_GETS_No_Mig [0 ] 0
+MT NC_DMA_GETS [0 ] 0
MT Invalidate [0 ] 0
MMT Load [0 ] 0
@@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0
MMT Other_GETS [0 ] 0
MMT Merged_GETS [0 ] 0
MMT Other_GETS_No_Mig [0 ] 0
+MMT NC_DMA_GETS [0 ] 0
MMT Invalidate [0 ] 0
Cache Stats: system.dir_cntrl0.probeFilter
@@ -502,19 +521,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1379
memory_reads: 1159
memory_writes: 220
- memory_refreshes: 434
- memory_total_request_delays: 471
- memory_delays_per_request: 0.341552
- memory_delays_in_input_queue: 15
+ memory_refreshes: 435
+ memory_total_request_delays: 495
+ memory_delays_per_request: 0.358956
+ memory_delays_in_input_queue: 3
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 456
- memory_stalls_for_bank_busy: 86
+ memory_delays_stalled_at_head_of_bank_queue: 492
+ memory_stalls_for_bank_busy: 124
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 30
+ memory_stalls_for_arbitration: 23
memory_stalls_for_bus: 78
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 262
+ memory_stalls_for_read_write_turnaround: 267
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
@@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0
NO_B_X UnblockS [0 ] 0
NO_B_X UnblockM [0 ] 0
NO_B_X Pf_Replacement [0 ] 0
+NO_B_X DMA_READ [0 ] 0
+NO_B_X DMA_WRITE [0 ] 0
NO_B_S GETX [0 ] 0
NO_B_S GETS [0 ] 0
@@ -648,6 +669,7 @@ O_B GETX [0 ] 0
O_B GETS [0 ] 0
O_B PUT [0 ] 0
O_B UnblockS [0 ] 0
+O_B UnblockM [0 ] 0
O_B Pf_Replacement [0 ] 0
O_B DMA_READ [0 ] 0
O_B DMA_WRITE [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 01467c4b7..968d521e0 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 5 2010 11:09:13
-M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates
-M5 started Aug 5 2010 11:09:30
+M5 compiled Feb 8 2011 17:56:59
+M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:57:03
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 207970 because target called exit()
+Exiting @ tick 208400 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 8112f9791..5f06bc32c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 31390 # Simulator instruction rate (inst/s)
-host_mem_usage 211076 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
-host_tick_rate 1018487 # Simulator tick rate (ticks/s)
+host_inst_rate 50833 # Simulator instruction rate (inst/s)
+host_mem_usage 214944 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 1651975 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000208 # Number of seconds simulated
-sim_ticks 207970 # Number of ticks simulated
+sim_ticks 208400 # Number of ticks simulated
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 2050 # DTB hits
@@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 207970 # number of cpu cycles simulated
+system.cpu.numCycles 208400 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 208400 # Number of busy cycles
+system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_fp_insts 10 # number of float instructions
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_refs 2060 # Number of memory references
+system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
+system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index a4ed53868..b7bfb0aae 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -186,6 +195,7 @@ tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
+access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 4efa8de79..594f80de9 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/13/2011 22:36:30
+Real time: Feb/08/2011 17:31:55
Profiler Stats
--------------
-Elapsed_time_in_seconds: 2
-Elapsed_time_in_minutes: 0.0333333
-Elapsed_time_in_hours: 0.000555556
-Elapsed_time_in_days: 2.31481e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.79
-Virtual_time_in_minutes: 0.0131667
-Virtual_time_in_hours: 0.000219444
-Virtual_time_in_days: 9.14352e-06
+Virtual_time_in_seconds: 0.39
+Virtual_time_in_minutes: 0.0065
+Virtual_time_in_hours: 0.000108333
+Virtual_time_in_days: 4.51389e-06
Ruby_current_time: 103637
Ruby_start_time: 0
Ruby_cycles: 103637
-mbytes_resident: 20.9219
-mbytes_total: 156.062
-resident_ratio: 0.134111
+mbytes_resident: 35.7188
+mbytes_total: 209.473
+resident_ratio: 0.170592
ruby_cycles_executed: [ 103638 ]
@@ -119,7 +119,7 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 6028
+page_reclaims: 10341
page_faults: 0
swaps: 0
block_inputs: 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index 5c8b35b72..38e786bad 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 13 2011 22:36:25
-M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
-M5 started Jan 13 2011 22:36:28
-M5 executing on scamorza.cs.wisc.edu
+M5 compiled Feb 8 2011 17:31:51
+M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:31:55
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 5b40ee1fb..591cdf9bb 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2534 # Simulator instruction rate (inst/s)
-host_mem_usage 159812 # Number of bytes of host memory used
-host_seconds 1.02 # Real time elapsed on the host
-host_tick_rate 101843 # Simulator tick rate (ticks/s)
+host_inst_rate 31237 # Simulator instruction rate (inst/s)
+host_mem_usage 214504 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 1253532 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000104 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 103637 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 103637 # Number of busy cycles
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 59f975e1e..dae855509 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -108,32 +117,19 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
-L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+children=L1DcacheMemory L1IcacheMemory
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
-[system.l1_cntrl0.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.l1_cntrl0.sequencer.dcache
-deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.l1_cntrl0.sequencer.dcache]
+[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=3
@@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.sequencer.icache]
+[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=3
@@ -177,14 +173,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
-debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@@ -194,13 +189,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -216,9 +216,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
-name=Crossbar
num_int_nodes=4
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 86aa94fb6..b0eff5788 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: Crossbar
+topology:
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Aug/05/2010 10:37:10
+Real time: Feb/08/2011 17:41:43
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.41
-Virtual_time_in_minutes: 0.00683333
-Virtual_time_in_hours: 0.000113889
-Virtual_time_in_days: 4.74537e-06
+Virtual_time_in_seconds: 0.4
+Virtual_time_in_minutes: 0.00666667
+Virtual_time_in_hours: 0.000111111
+Virtual_time_in_days: 4.62963e-06
Ruby_current_time: 85988
Ruby_start_time: 0
Ruby_cycles: 85988
-mbytes_resident: 33.6484
-mbytes_total: 33.6562
-resident_ratio: 1
+mbytes_resident: 35.8359
+mbytes_total: 209.617
+resident_ratio: 0.171015
ruby_cycles_executed: [ 85989 ]
@@ -119,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7386
-page_faults: 2090
+page_reclaims: 10362
+page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.342645
outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.sequencer.icache
- system.l1_cntrl0.sequencer.icache_total_misses: 0
- system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
- system.l1_cntrl0.sequencer.icache_total_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+ system.l1_cntrl0.L1IcacheMemory_total_misses: 0
+ system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
-Cache Stats: system.l1_cntrl0.sequencer.dcache
- system.l1_cntrl0.sequencer.dcache_total_misses: 0
- system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
- system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+ system.l1_cntrl0.L1DcacheMemory_total_misses: 0
+ system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+ system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
--- L1Cache ---
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index c8e6b0646..2588731f1 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 5 2010 10:34:54
-M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
-M5 started Aug 5 2010 10:37:10
-M5 executing on svvint09
+M5 compiled Feb 8 2011 17:41:34
+M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:41:42
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index bc9801bf7..dd02fbf60 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 19822 # Simulator instruction rate (inst/s)
-host_mem_usage 211548 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 661411 # Simulator tick rate (ticks/s)
+host_inst_rate 26760 # Simulator instruction rate (inst/s)
+host_mem_usage 214652 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 891261 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000086 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 85988 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 85988 # Number of busy cycles
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 1971d2a44..537819260 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,9 +120,9 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
-L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+children=L1DcacheMemory L1IcacheMemory
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
buffer_size=0
dynamic_timeout_enabled=true
@@ -125,24 +134,11 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
-[system.l1_cntrl0.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.l1_cntrl0.sequencer.dcache
-deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.l1_cntrl0.sequencer.dcache]
+[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=2
@@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.sequencer.icache]
+[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=2
@@ -188,14 +184,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
-debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@@ -205,13 +200,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -227,9 +227,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
-name=Crossbar
num_int_nodes=4
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index dbdcc6601..23d0a1d6f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: Crossbar
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Aug/05/2010 10:43:25
+Real time: Feb/08/2011 17:51:05
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.25
-Virtual_time_in_minutes: 0.00416667
-Virtual_time_in_hours: 6.94444e-05
-Virtual_time_in_days: 2.89352e-06
+Virtual_time_in_seconds: 0.33
+Virtual_time_in_minutes: 0.0055
+Virtual_time_in_hours: 9.16667e-05
+Virtual_time_in_days: 3.81944e-06
Ruby_current_time: 92099
Ruby_start_time: 0
Ruby_cycles: 92099
-mbytes_resident: 33.5859
-mbytes_total: 33.5938
-resident_ratio: 1
+mbytes_resident: 35.7695
+mbytes_total: 209.457
+resident_ratio: 0.17081
ruby_cycles_executed: [ 92100 ]
@@ -127,8 +127,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7341
-page_faults: 2084
+page_reclaims: 10334
+page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739
outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.sequencer.icache
- system.l1_cntrl0.sequencer.icache_total_misses: 270
- system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
- system.l1_cntrl0.sequencer.icache_total_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+ system.l1_cntrl0.L1IcacheMemory_total_misses: 270
+ system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
+ system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+ system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
- system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
+ system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100%
-Cache Stats: system.l1_cntrl0.sequencer.dcache
- system.l1_cntrl0.sequencer.dcache_total_misses: 243
- system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243
- system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+ system.l1_cntrl0.L1DcacheMemory_total_misses: 243
+ system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243
+ system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971%
- system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029%
+ system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971%
+ system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029%
- system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100%
+ system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100%
--- L1Cache ---
- Event Counts -
@@ -222,7 +222,7 @@ Load [415 ] 415
Ifetch [2585 ] 2585
Store [294 ] 294
Atomic [0 ] 0
-L1_Replacement [506 ] 506
+L1_Replacement [503 ] 503
Data_Shared [18 ] 18
Data_Owner [0 ] 0
Data_All_Tokens [495 ] 495
@@ -352,7 +352,7 @@ M_W Load [47 ] 47
M_W Ifetch [1038 ] 1038
M_W Store [6 ] 6
M_W Atomic [0 ] 0
-M_W L1_Replacement [4 ] 4
+M_W L1_Replacement [1 ] 1
M_W Transient_GETX [0 ] 0
M_W Transient_Local_GETX [0 ] 0
M_W Transient_GETS [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 9cf458143..f29df4a71 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 5 2010 10:41:36
-M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
-M5 started Aug 5 2010 10:43:25
-M5 executing on svvint09
+M5 compiled Feb 8 2011 17:50:56
+M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:51:05
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e8b218502..caef5b8f0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 42948 # Simulator instruction rate (inst/s)
-host_mem_usage 211392 # Number of bytes of host memory used
+host_inst_rate 44139 # Simulator instruction rate (inst/s)
+host_mem_usage 214488 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 1534907 # Simulator tick rate (ticks/s)
+host_tick_rate 1572917 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000092 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 92099 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 92099 # Number of busy cycles
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 4d36728d7..08f882272 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -70,6 +79,7 @@ type=Directory_Controller
children=directory memBuffer probeFilter
buffer_size=0
directory=system.dir_cntrl0.directory
+full_bit_dir_enabled=false
memBuffer=system.dir_cntrl0.memBuffer
memory_controller_latency=2
number_of_TBEs=256
@@ -118,17 +128,18 @@ start_index_bit=6
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L2cacheMemory sequencer
-L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
-L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+children=L2cacheMemory
+L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
+L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
buffer_size=0
cache_response_latency=10
issue_latency=2
+l2_cache_hit_latency=10
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
@@ -140,12 +151,37 @@ replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
-[system.l1_cntrl0.sequencer]
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.cpu_ruby_ports.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=cpu_ruby_ports network profiler tracer
+block_size_bytes=64
+clock=1
+mem_size=134217728
+network=system.ruby.network
+no_mem_vec=false
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache icache
-dcache=system.l1_cntrl0.sequencer.dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
+icache=system.ruby.cpu_ruby_ports.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
@@ -153,7 +189,7 @@ version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
-[system.l1_cntrl0.sequencer.dcache]
+[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=2
@@ -161,7 +197,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.sequencer.icache]
+[system.ruby.cpu_ruby_ports.icache]
type=RubyCache
assoc=2
latency=2
@@ -169,39 +205,6 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
-
-[system.ruby]
-type=RubySystem
-children=debug network profiler tracer
-block_size_bytes=64
-clock=1
-debug=system.ruby.debug
-mem_size=134217728
-network=system.ruby.network
-no_mem_vec=false
-profiler=system.ruby.profiler
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
-
[system.ruby.network]
type=SimpleNetwork
children=topology
@@ -216,9 +219,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-name=Crossbar
num_int_nodes=3
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index 6e53a933a..3e0d391db 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: Crossbar
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Aug/05/2010 14:44:19
+Real time: Feb/08/2011 17:57:03
Profiler Stats
--------------
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.21
-Virtual_time_in_minutes: 0.0035
-Virtual_time_in_hours: 5.83333e-05
-Virtual_time_in_days: 2.43056e-06
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours: 9.44444e-05
+Virtual_time_in_days: 3.93519e-06
-Ruby_current_time: 78408
+Ruby_current_time: 78448
Ruby_start_time: 0
-Ruby_cycles: 78408
+Ruby_cycles: 78448
-mbytes_resident: 33.3242
-mbytes_total: 33.332
-resident_ratio: 1
+mbytes_resident: 35.3906
+mbytes_total: 208.879
+resident_ratio: 0.169469
-ruby_cycles_executed: [ 78409 ]
+ruby_cycles_executed: [ 78449 ]
Busy Controller Counts:
L1Cache-0:0
@@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
-miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
+miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
-miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
-miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
+miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 440
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
-miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
-miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
-miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
+miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
-miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
-miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
+miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -126,8 +126,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7298
-page_faults: 2071
+page_reclaims: 10290
+page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -144,9 +144,9 @@ total_msgs: 7791 total_bytes: 162552
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.110878
- links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.110822
+ links_utilized_percent_switch_0_link_0: 0.0700145 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.151629 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
@@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.110878
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.159064
- links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.158983
+ links_utilized_percent_switch_1_link_0: 0.0379073 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.280058 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
@@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.159064
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.215954
- links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.215844
+ links_utilized_percent_switch_2_link_0: 0.280058 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.151629 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
@@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215954
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.sequencer.icache
- system.l1_cntrl0.sequencer.icache_total_misses: 270
- system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
- system.l1_cntrl0.sequencer.icache_total_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.ruby.cpu_ruby_ports.icache
+ system.ruby.cpu_ruby_ports.icache_total_misses: 270
+ system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270
+ system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
+ system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
+ system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+ system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
- system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
+ system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 270 100%
-Cache Stats: system.l1_cntrl0.sequencer.dcache
- system.l1_cntrl0.sequencer.dcache_total_misses: 240
- system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240
- system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+Cache Stats: system.ruby.cpu_ruby_ports.dcache
+ system.ruby.cpu_ruby_ports.dcache_total_misses: 240
+ system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240
+ system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
+ system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
+ system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333%
- system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667%
+ system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333%
+ system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667%
- system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100%
+ system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 240 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory
- system.l1_cntrl0.L2cacheMemory_total_misses: 441
- system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441
+ system.l1_cntrl0.L2cacheMemory_total_misses: 510
+ system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066%
- system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576%
- system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358%
+ system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863%
+ system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725%
+ system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412%
- system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100%
+ system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 510 100%
--- L1Cache ---
- Event Counts -
-Load [428 ] 428
-Ifetch [2597 ] 2597
-Store [302 ] 302
+Load [422 ] 422
+Ifetch [2591 ] 2591
+Store [298 ] 298
L2_Replacement [425 ] 425
L1_to_L2 [502 ] 502
Trigger_L2_to_L1D [47 ] 47
@@ -231,6 +231,7 @@ Other_GETX [0 ] 0
Other_GETS [0 ] 0
Merged_GETS [0 ] 0
Other_GETS_No_Mig [0 ] 0
+NC_DMA_GETS [0 ] 0
Invalidate [0 ] 0
Ack [0 ] 0
Shared_Ack [0 ] 0
@@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0
I Other_GETX [0 ] 0
I Other_GETS [0 ] 0
I Other_GETS_No_Mig [0 ] 0
+I NC_DMA_GETS [0 ] 0
I Invalidate [0 ] 0
S Load [0 ] 0
@@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0
S Other_GETX [0 ] 0
S Other_GETS [0 ] 0
S Other_GETS_No_Mig [0 ] 0
+S NC_DMA_GETS [0 ] 0
S Invalidate [0 ] 0
O Load [0 ] 0
@@ -278,6 +281,7 @@ O Other_GETX [0 ] 0
O Other_GETS [0 ] 0
O Merged_GETS [0 ] 0
O Other_GETS_No_Mig [0 ] 0
+O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
M Load [131 ] 131
@@ -291,6 +295,7 @@ M Other_GETX [0 ] 0
M Other_GETS [0 ] 0
M Merged_GETS [0 ] 0
M Other_GETS_No_Mig [0 ] 0
+M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0
MM Load [138 ] 138
@@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0
MM Other_GETS_No_Mig [0 ] 0
+MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0
IM Load [0 ] 0
@@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0
IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0
+IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0
IM Ack [0 ] 0
IM Data [0 ] 0
@@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0
SM Other_GETX [0 ] 0
SM Other_GETS [0 ] 0
SM Other_GETS_No_Mig [0 ] 0
+SM NC_DMA_GETS [0 ] 0
SM Invalidate [0 ] 0
SM Ack [0 ] 0
SM Data [0 ] 0
+SM Exclusive_Data [0 ] 0
OM Load [0 ] 0
OM Ifetch [0 ] 0
@@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0
OM Other_GETS [0 ] 0
OM Merged_GETS [0 ] 0
OM Other_GETS_No_Mig [0 ] 0
+OM NC_DMA_GETS [0 ] 0
OM Invalidate [0 ] 0
OM Ack [0 ] 0
OM All_acks [0 ] 0
@@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0
IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0
+IS NC_DMA_GETS [0 ] 0
IS Invalidate [0 ] 0
IS Ack [0 ] 0
IS Shared_Ack [0 ] 0
@@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0
OI Other_GETS [0 ] 0
OI Merged_GETS [0 ] 0
OI Other_GETS_No_Mig [0 ] 0
+OI NC_DMA_GETS [0 ] 0
OI Invalidate [0 ] 0
OI Writeback_Ack [0 ] 0
-MI Load [13 ] 13
-MI Ifetch [12 ] 12
-MI Store [8 ] 8
+MI Load [7 ] 7
+MI Ifetch [6 ] 6
+MI Store [4 ] 4
MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0
MI Other_GETS [0 ] 0
MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0
+MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0
MI Writeback_Ack [425 ] 425
@@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0
II Other_GETX [0 ] 0
II Other_GETS [0 ] 0
II Other_GETS_No_Mig [0 ] 0
+II NC_DMA_GETS [0 ] 0
II Invalidate [0 ] 0
II Writeback_Ack [0 ] 0
II Writeback_Nack [0 ] 0
@@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0
IT Other_GETS [0 ] 0
IT Merged_GETS [0 ] 0
IT Other_GETS_No_Mig [0 ] 0
+IT NC_DMA_GETS [0 ] 0
IT Invalidate [0 ] 0
ST Load [0 ] 0
@@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0
ST Other_GETS [0 ] 0
ST Merged_GETS [0 ] 0
ST Other_GETS_No_Mig [0 ] 0
+ST NC_DMA_GETS [0 ] 0
ST Invalidate [0 ] 0
OT Load [0 ] 0
@@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0
OT Other_GETS [0 ] 0
OT Merged_GETS [0 ] 0
OT Other_GETS_No_Mig [0 ] 0
+OT NC_DMA_GETS [0 ] 0
OT Invalidate [0 ] 0
MT Load [0 ] 0
@@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0
MT Other_GETS [0 ] 0
MT Merged_GETS [0 ] 0
MT Other_GETS_No_Mig [0 ] 0
+MT NC_DMA_GETS [0 ] 0
MT Invalidate [0 ] 0
MMT Load [0 ] 0
@@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0
MMT Other_GETS [0 ] 0
MMT Merged_GETS [0 ] 0
MMT Other_GETS_No_Mig [0 ] 0
+MMT NC_DMA_GETS [0 ] 0
MMT Invalidate [0 ] 0
Cache Stats: system.dir_cntrl0.probeFilter
@@ -503,18 +522,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_reads: 441
memory_writes: 81
memory_refreshes: 164
- memory_total_request_delays: 147
- memory_delays_per_request: 0.281609
+ memory_total_request_delays: 151
+ memory_delays_per_request: 0.289272
memory_delays_in_input_queue: 2
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 145
- memory_stalls_for_bank_busy: 27
+ memory_delays_stalled_at_head_of_bank_queue: 149
+ memory_stalls_for_bank_busy: 22
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 6
- memory_stalls_for_bus: 23
+ memory_stalls_for_arbitration: 7
+ memory_stalls_for_bus: 26
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 89
+ memory_stalls_for_read_write_turnaround: 94
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
@@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0
NO_B_X UnblockS [0 ] 0
NO_B_X UnblockM [0 ] 0
NO_B_X Pf_Replacement [0 ] 0
+NO_B_X DMA_READ [0 ] 0
+NO_B_X DMA_WRITE [0 ] 0
NO_B_S GETX [0 ] 0
NO_B_S GETS [0 ] 0
@@ -648,6 +669,7 @@ O_B GETX [0 ] 0
O_B GETS [0 ] 0
O_B PUT [0 ] 0
O_B UnblockS [0 ] 0
+O_B UnblockM [0 ] 0
O_B Pf_Replacement [0 ] 0
O_B DMA_READ [0 ] 0
O_B DMA_WRITE [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 76a97a409..06957aba3 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 5 2010 14:43:33
-M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
-M5 started Aug 5 2010 14:44:19
-M5 executing on svvint09
+M5 compiled Feb 8 2011 17:56:59
+M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:57:03
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 78408 because target called exit()
+Exiting @ tick 78448 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 58de899ed..73743c0c5 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 42947 # Simulator instruction rate (inst/s)
-host_mem_usage 211060 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 1306713 # Simulator tick rate (ticks/s)
+host_inst_rate 49095 # Simulator instruction rate (inst/s)
+host_mem_usage 213896 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 1489708 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000078 # Number of seconds simulated
-sim_ticks 78408 # Number of ticks simulated
+sim_ticks 78448 # Number of ticks simulated
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 709 # DTB hits
@@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 78408 # number of cpu cycles simulated
+system.cpu.numCycles 78448 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 78448 # Number of busy cycles
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------