summaryrefslogtreecommitdiff
path: root/tests/quick/00.hello
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2009-06-09 23:55:53 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-06-09 23:55:53 -0700
commit85ca50261101287c33539adeb703b21a3783a703 (patch)
tree823b2fc9bb43d9c5cabdce23aa147e511755a35e /tests/quick/00.hello
parentd91a3cf53d7077aa70e5bf101aab68e7b1ebd579 (diff)
downloadgem5-85ca50261101287c33539adeb703b21a3783a703.tar.xz
ARM: Add a hello world regression.
Diffstat (limited to 'tests/quick/00.hello')
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini91
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simout17
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt36
4 files changed, 149 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..fdc787e7b
--- /dev/null
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,91 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+UnifiedTLB=true
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..a2692a6c9
--- /dev/null
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero.
+For more information see: http://www.m5sim.org/warn/3a2134f6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..40fbf355d
--- /dev/null
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jun 9 2009 23:46:33
+M5 revision 6639f3c716a6 6238 default qtip tip armreg.patch qbase
+M5 started Jun 9 2009 23:53:49
+M5 executing on fajita
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 2299000 because target called exit()
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..5a17d118e
--- /dev/null
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,36 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 79163 # Simulator instruction rate (inst/s)
+host_mem_usage 189980 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 39442081 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 4598 # Number of instructions simulated
+sim_seconds 0.000002 # Number of seconds simulated
+sim_ticks 2299000 # Number of ticks simulated
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 4599 # number of cpu cycles simulated
+system.cpu.num_insts 4598 # Number of instructions executed
+system.cpu.num_refs 1851 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 14 # Number of system calls
+
+---------- End Simulation Statistics ----------