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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:22:34 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:22:34 -0400 |
| commit | 272d867402e50dba49f1f78976711388a8056427 (patch) | |
| tree | 4542f12377fae4e2f31a592b161997487856cd74 /tests/quick/00.hello | |
| parent | d2a4f595d6e70f5f9f5c7cae4f496c2db1e39ca5 (diff) | |
| download | gem5-272d867402e50dba49f1f78976711388a8056427.tar.xz | |
Update statistics for the last three revisions
--HG--
extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24
Diffstat (limited to 'tests/quick/00.hello')
9 files changed, 50 insertions, 54 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index ce1ae8d6f..00f26425a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 409 # Nu global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted global.BPredUnit.lookups 2029 # Number of BP lookups global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target. -host_inst_rate 9351 # Simulator instruction rate (inst/s) -host_mem_usage 180452 # Number of bytes of host memory used -host_seconds 0.60 # Real time elapsed on the host -host_tick_rate 7988790 # Simulator tick rate (ticks/s) +host_inst_rate 84357 # Simulator instruction rate (inst/s) +host_mem_usage 197344 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 71887995 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. memdepunit.memDep.conflictingStores 124 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2030 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 17 # Th system.cpu.commit.commitSquashedInsts 4234 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.680420 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.680420 # CPI: Total CPI of All Threads +system.cpu.cpi 1.709586 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.709586 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6357.142857 # average ReadReq mshr miss latency @@ -152,10 +152,10 @@ system.cpu.fetch.Cycles 3746 # Nu system.cpu.fetch.IcacheSquashes 226 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 12519 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.214732 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.211068 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1542 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.324902 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.302299 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 9449 system.cpu.fetch.rateDist.min_value 0 @@ -234,10 +234,10 @@ system.cpu.icache.tagsinuse 164.253671 # Cy system.cpu.icache.total_refs 1211 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 110443 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 1199 # Number of branches executed system.cpu.iew.EXEC:nop 72 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.848450 # Inst execution rate +system.cpu.iew.EXEC:rate 0.833975 # Inst execution rate system.cpu.iew.EXEC:refs 2660 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1006 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -247,7 +247,7 @@ system.cpu.iew.WB:fanout 0.742905 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 4031 # num instructions producing a value -system.cpu.iew.WB:rate 0.811091 # insts written-back per cycle +system.cpu.iew.WB:rate 0.797254 # insts written-back per cycle system.cpu.iew.WB:sent 7781 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking @@ -277,8 +277,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 424 # system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.595089 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.595089 # IPC: Total IPC of All Threads +system.cpu.ipc 0.584937 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.584937 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8383 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued @@ -329,7 +329,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.887184 # Inst issue rate +system.cpu.iq.ISSUE:rate 0.872048 # Inst issue rate system.cpu.iq.iqInstsAdded 9901 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8383 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ @@ -421,7 +421,7 @@ system.cpu.l2cache.tagsinuse 218.025629 # Cy system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 9449 # number of cpu cycles simulated +system.cpu.numCycles 9613 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 6291 # Number of cycles rename is idle diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 0908a82c9..51a854d5e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 243703 # Simulator instruction rate (inst/s) -host_mem_usage 179944 # Number of bytes of host memory used +host_inst_rate 341217 # Simulator instruction rate (inst/s) +host_mem_usage 196644 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 781539770 # Simulator tick rate (ticks/s) +host_tick_rate 1094407052 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5641 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated @@ -240,7 +240,7 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18374000 # number of cpu cycles simulated +system.cpu.numCycles 36748 # number of cpu cycles simulated system.cpu.num_insts 5641 # Number of instructions executed system.cpu.num_refs 1801 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index ffd2f7ab7..5d4ecfb70 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 213 # Nu global.BPredUnit.condPredicted 401 # Number of conditional branches predicted global.BPredUnit.lookups 824 # Number of BP lookups global.BPredUnit.usedRAS 163 # Number of times the RAS was used to get a target. -host_inst_rate 31893 # Simulator instruction rate (inst/s) -host_mem_usage 179460 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 32096529 # Simulator tick rate (ticks/s) +host_inst_rate 66708 # Simulator instruction rate (inst/s) +host_mem_usage 196356 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 66966767 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 698 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 4 # Th system.cpu.commit.commitSquashedInsts 1380 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.984080 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.984080 # CPI: Total CPI of All Threads +system.cpu.cpi 2.019690 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.019690 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 8639.344262 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5655.737705 # average ReadReq mshr miss latency @@ -152,10 +152,10 @@ system.cpu.fetch.Cycles 1626 # Nu system.cpu.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 5268 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 242 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.173986 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.170919 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 707 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 319 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.112331 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.092719 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 4736 system.cpu.fetch.rateDist.min_value 0 @@ -234,10 +234,10 @@ system.cpu.icache.tagsinuse 92.900452 # Cy system.cpu.icache.total_refs 510 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 56472 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 85 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 538 # Number of branches executed system.cpu.iew.EXEC:nop 274 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.670608 # Inst execution rate +system.cpu.iew.EXEC:rate 0.658784 # Inst execution rate system.cpu.iew.EXEC:refs 934 # number of memory reference insts executed system.cpu.iew.EXEC:stores 356 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -247,7 +247,7 @@ system.cpu.iew.WB:fanout 0.794497 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 1415 # num instructions producing a value -system.cpu.iew.WB:rate 0.651182 # insts written-back per cycle +system.cpu.iew.WB:rate 0.639701 # insts written-back per cycle system.cpu.iew.WB:sent 3123 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 149 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking @@ -277,8 +277,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 118 # system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.504012 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.504012 # IPC: Total IPC of All Threads +system.cpu.ipc 0.495125 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.495125 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 3281 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -329,7 +329,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.692779 # Inst issue rate +system.cpu.iq.ISSUE:rate 0.680564 # Inst issue rate system.cpu.iq.iqInstsAdded 3776 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3281 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ @@ -420,7 +420,7 @@ system.cpu.l2cache.tagsinuse 115.687599 # Cy system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 4736 # number of cpu cycles simulated +system.cpu.numCycles 4821 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 3552 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 89de75b41..d906bb79e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 17:36:58 -M5 started Tue Aug 14 17:40:04 2007 -M5 executing on nacho +M5 compiled Sep 27 2007 13:46:37 +M5 started Thu Sep 27 20:06:36 2007 +M5 executing on zeep command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 942cc1b79..60bfb7de8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123219 # Simulator instruction rate (inst/s) -host_mem_usage 178996 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 443932267 # Simulator tick rate (ticks/s) +host_inst_rate 178240 # Simulator instruction rate (inst/s) +host_mem_usage 195696 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 641473527 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000009 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9438000 # number of cpu cycles simulated +system.cpu.numCycles 18876 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index cb408c2ca..c7e605dd3 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 186969 # Simulator instruction rate (inst/s) -host_mem_usage 180780 # Number of bytes of host memory used +host_inst_rate 192479 # Simulator instruction rate (inst/s) +host_mem_usage 197496 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 602814418 # Simulator tick rate (ticks/s) +host_tick_rate 618816195 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated @@ -224,7 +224,7 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18463000 # number of cpu cycles simulated +system.cpu.numCycles 36926 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr index 7873672f2..87866a2a5 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr @@ -1,3 +1 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index ff4bd3dbe..b81236150 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198489 # Simulator instruction rate (inst/s) -host_mem_usage 181156 # Number of bytes of host memory used +host_inst_rate 290934 # Simulator instruction rate (inst/s) +host_mem_usage 197920 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 645076356 # Simulator tick rate (ticks/s) +host_tick_rate 939694341 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4833 # Number of instructions simulated sim_seconds 0.000016 # Number of seconds simulated @@ -224,7 +224,7 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15925000 # number of cpu cycles simulated +system.cpu.numCycles 31850 # number of cpu cycles simulated system.cpu.num_insts 4833 # Number of instructions executed system.cpu.num_refs 1282 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr index 7873672f2..87866a2a5 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... |