diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-04-15 13:13:58 -0700 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-04-15 13:13:58 -0700 |
commit | 48d4ca522a2f771188d93a2d5ff54cf505a8ca41 (patch) | |
tree | 5e982be7b07ed178d27097039a7645be62da890f /tests/quick/00.hello | |
parent | 8882dc1283771463a20194c083f4b8940a2d574b (diff) | |
download | gem5-48d4ca522a2f771188d93a2d5ff54cf505a8ca41.tar.xz |
Update stats after elimination of Unallocated state.
Somehow ending threads with halt() instead of deallocate()
reduces the squash count on o3 by 1 (and a few other
similarly trivial changes).
Diffstat (limited to 'tests/quick/00.hello')
6 files changed, 32 insertions, 32 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 7eb74398a..be9b35776 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -361,7 +361,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 3b9bfb958..7b43e6682 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:44:12 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled Apr 14 2009 16:03:56 +M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update +M5 started Apr 14 2009 16:03:59 +M5 executing on phenom +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index b0e90083c..59870a0d4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 62049 # Simulator instruction rate (inst/s) -host_mem_usage 202540 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 120907399 # Simulator tick rate (ticks/s) +host_inst_rate 100618 # Simulator instruction rate (inst/s) +host_mem_usage 204352 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 195881226 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -19,10 +19,10 @@ system.cpu.BPredUnit.usedRAS 304 # Nu system.cpu.commit.COM:branches 1051 # Number of branches committed system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12417 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 9513 76.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9514 76.62% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% # Number of insts commited each cycle @@ -32,10 +32,10 @@ system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 115 0.93% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12417 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515706 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.304935 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515664 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.304890 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 1802 # Nu system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 501 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index a1f81629d..477ca365f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -361,7 +361,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 19ff35ac6..0ffb13f0d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:44:10 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing +M5 compiled Apr 14 2009 16:03:56 +M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update +M5 started Apr 14 2009 16:03:59 +M5 executing on phenom +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 4b2eade71..220cf8ff6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 53715 # Simulator instruction rate (inst/s) -host_mem_usage 201548 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 160751052 # Simulator tick rate (ticks/s) +host_inst_rate 72174 # Simulator instruction rate (inst/s) +host_mem_usage 203356 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 215783466 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -19,10 +19,10 @@ system.cpu.BPredUnit.usedRAS 165 # Nu system.cpu.commit.COM:branches 396 # Number of branches committed system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6196 +system.cpu.commit.COM:committed_per_cycle::samples 6197 system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::0-1 5239 84.55% +system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% @@ -32,10 +32,10 @@ system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% system.cpu.commit.COM:committed_per_cycle::8 38 0.61% system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::total 6196 +system.cpu.commit.COM:committed_per_cycle::total 6197 system.cpu.commit.COM:committed_per_cycle::max_value 8 -system.cpu.commit.COM:committed_per_cycle::mean 0.415752 -system.cpu.commit.COM:committed_per_cycle::stdev 1.208059 +system.cpu.commit.COM:committed_per_cycle::mean 0.415685 +system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 747 # Nu system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 239 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken |