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authorNathan Binkert <nate@binkert.org>2009-04-08 22:21:30 -0700
committerNathan Binkert <nate@binkert.org>2009-04-08 22:21:30 -0700
commit374ba9bae359e68c1496f8db25c38a817af2da19 (patch)
tree48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/00.hello
parente0de2c34433be76eac7798e58e1ae02f5bffb732 (diff)
downloadgem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/00.hello')
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/o3-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt40
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-atomic/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt38
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt40
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt40
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt40
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt40
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-atomic/simout10
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt26
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini12
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt26
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-atomic/simout10
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic/simout10
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini4
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing/simout10
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt8
36 files changed, 275 insertions, 227 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 46ef9d2b9..7eb74398a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index f448ee025..3b9bfb958 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar 6 2009 18:22:19
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:44:12
M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 21437f2a4..b0e90083c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 83921 # Simulator instruction rate (inst/s)
-host_mem_usage 202572 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 163392144 # Simulator tick rate (ticks/s)
+host_inst_rate 62049 # Simulator instruction rate (inst/s)
+host_mem_usage 202540 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 120907399 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6386 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 2366 # Nu
system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 2951 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2890 # DTB hits
-system.cpu.dtb.misses 61 # DTB misses
+system.cpu.dtb.data_accesses 2951 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2890 # DTB hits
+system.cpu.dtb.data_misses 61 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 1876 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 1840 # DTB read hits
@@ -321,10 +325,22 @@ system.cpu.iq.iqSquashedInstsExamined 4189 # Nu
system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 1838 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 1802 # ITB hits
-system.cpu.itb.misses 36 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 1838 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 1802 # ITB hits
+system.cpu.itb.fetch_misses 36 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 5b4a31473..adc37d29a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index 8975ff812..da206d16c 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py quick/00.hello/alpha/linux/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:37:48
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 93917b1eb..a6c36497f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 122377 # Simulator instruction rate (inst/s)
-host_mem_usage 192524 # Number of bytes of host memory used
+host_inst_rate 130449 # Simulator instruction rate (inst/s)
+host_mem_usage 194292 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 61135620 # Simulator tick rate (ticks/s)
+host_tick_rate 65193146 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 3215000 # Number of ticks simulated
-system.cpu.dtb.accesses 2060 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2050 # DTB hits
-system.cpu.dtb.misses 10 # DTB misses
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 1185 # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 6431 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 6414 # ITB hits
-system.cpu.itb.misses 17 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6414 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 6431 # number of cpu cycles simulated
system.cpu.num_insts 6404 # Number of instructions executed
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 26edcc7cf..988a9a0ce 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index 22d348b2d..fd7224cc6 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py quick/00.hello/alpha/linux/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index dc4411624..14eb9b58a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 344098 # Simulator instruction rate (inst/s)
-host_mem_usage 199968 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 1795121173 # Simulator tick rate (ticks/s)
+host_inst_rate 14499 # Simulator instruction rate (inst/s)
+host_mem_usage 201828 # Number of bytes of host memory used
+host_seconds 0.44 # Real time elapsed on the host
+host_tick_rate 76395737 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000034 # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 104.111261 # Cy
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 2060 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2050 # DTB hits
-system.cpu.dtb.misses 10 # DTB misses
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 1185 # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs 6136 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 6432 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 6415 # ITB hits
-system.cpu.itb.misses 17 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6415 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 9abe15dfc..a1f81629d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index 038644e5f..19ff35ac6 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar 6 2009 18:16:36
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:44:10
M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 14b605eaa..4b2eade71 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 39458 # Simulator instruction rate (inst/s)
-host_mem_usage 201572 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 118256203 # Simulator tick rate (ticks/s)
+host_inst_rate 53715 # Simulator instruction rate (inst/s)
+host_mem_usage 201548 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 160751052 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000007 # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 929 # Nu
system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 971 # DTB accesses
-system.cpu.dtb.acv 1 # DTB access violations
-system.cpu.dtb.hits 946 # DTB hits
-system.cpu.dtb.misses 25 # DTB misses
+system.cpu.dtb.data_accesses 971 # DTB accesses
+system.cpu.dtb.data_acv 1 # DTB access violations
+system.cpu.dtb.data_hits 946 # DTB hits
+system.cpu.dtb.data_misses 25 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 611 # DTB read accesses
system.cpu.dtb.read_acv 1 # DTB read access violations
system.cpu.dtb.read_hits 600 # DTB read hits
@@ -321,10 +325,22 @@ system.cpu.iq.iqSquashedInstsExamined 1447 # Nu
system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 776 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 747 # ITB hits
-system.cpu.itb.misses 29 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 776 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 747 # ITB hits
+system.cpu.itb.fetch_misses 29 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 8ca1fff45..255dbd855 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 7c13e1d4c..fd4dcc4fc 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py quick/00.hello/alpha/tru64/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index ddfd1ad69..fc21ca705 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 147781 # Simulator instruction rate (inst/s)
-host_mem_usage 191596 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 73371409 # Simulator tick rate (ticks/s)
+host_inst_rate 7782 # Simulator instruction rate (inst/s)
+host_mem_usage 193364 # Number of bytes of host memory used
+host_seconds 0.33 # Real time elapsed on the host
+host_tick_rate 3915244 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 1297500 # Number of ticks simulated
-system.cpu.dtb.accesses 717 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 709 # DTB hits
-system.cpu.dtb.misses 8 # DTB misses
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 415 # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 2596 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 2585 # ITB hits
-system.cpu.itb.misses 11 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2596 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2585 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2596 # number of cpu cycles simulated
system.cpu.num_insts 2577 # Number of instructions executed
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index f0bdf09de..be492f6c5 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 3560f6496..ac591190c 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 5c25b785f..da1cac32f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 73131 # Simulator instruction rate (inst/s)
-host_mem_usage 199016 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 490513834 # Simulator tick rate (ticks/s)
+host_inst_rate 6492 # Simulator instruction rate (inst/s)
+host_mem_usage 200880 # Number of bytes of host memory used
+host_seconds 0.40 # Real time elapsed on the host
+host_tick_rate 43734802 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 47.575114 # Cy
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 717 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 709 # DTB hits
-system.cpu.dtb.misses 8 # DTB misses
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 415 # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs 2423 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 2597 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 2586 # ITB hits
-system.cpu.itb.misses 11 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 766c4f486..5d677c743 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tlb tracer workload
+children=dtb itb tracer workload
CP0_Config=0
CP0_Config1=0
CP0_Config1_C2=false
@@ -66,7 +66,6 @@ CP0_PerfCtr_M=false
CP0_PerfCtr_W=false
CP0_SrsCtl_HSS=0
CP0_WatchHi_M=false
-UnifiedTLB=true
checker=Null
clock=500
cpu_id=0
@@ -87,7 +86,6 @@ progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
-tlb=system.cpu.tlb
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
@@ -95,15 +93,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=MipsDTB
+type=MipsTLB
size=64
[system.cpu.itb]
-type=MipsITB
-size=64
-
-[system.cpu.tlb]
-type=MipsUTB
+type=MipsTLB
size=64
[system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 7b1955a4b..4fee53c4d 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:16:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:16:42
-M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py quick/00.hello/mips/linux/simple-atomic
+M5 compiled Apr 8 2009 12:30:01
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:33:27
+M5 executing on maize
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 20921ce17..a50f65423 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 24803 # Simulator instruction rate (inst/s)
-host_mem_usage 193824 # Number of bytes of host memory used
-host_seconds 0.23 # Real time elapsed on the host
-host_tick_rate 12384497 # Simulator tick rate (ticks/s)
+host_inst_rate 113529 # Simulator instruction rate (inst/s)
+host_mem_usage 195572 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 56492209 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5656 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
@@ -31,24 +31,6 @@ system.cpu.not_idle_fraction 1 # Pe
system.cpu.numCycles 5657 # number of cpu cycles simulated
system.cpu.num_insts 5656 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_misses 0 # DTB write misses
-system.cpu.tlb.write_misses 0 # DTB write misses
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index d6fb3e91a..ac73fcc0d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache tlb toL2Bus tracer workload
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
CP0_Config=0
CP0_Config1=0
CP0_Config1_C2=false
@@ -66,7 +66,6 @@ CP0_PerfCtr_M=false
CP0_PerfCtr_W=false
CP0_SrsCtl_HSS=0
CP0_WatchHi_M=false
-UnifiedTLB=true
checker=Null
clock=500
cpu_id=0
@@ -85,7 +84,6 @@ numThreads=1
phase=0
progress_interval=0
system=system
-tlb=system.cpu.tlb
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -124,7 +122,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=MipsDTB
+type=MipsTLB
size=64
[system.cpu.icache]
@@ -160,7 +158,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=MipsITB
+type=MipsTLB
size=64
[system.cpu.l2cache]
@@ -195,10 +193,6 @@ write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
mem_side=system.membus.port[1]
-[system.cpu.tlb]
-type=MipsUTB
-size=64
-
[system.cpu.toL2Bus]
type=Bus
block_size=64
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index a5bd2cd4d..77ad52898 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:16:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:16:42
-M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py quick/00.hello/mips/linux/simple-timing
+M5 compiled Apr 8 2009 12:30:01
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:04
+M5 executing on maize
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index de10d4a74..c7fdc027e 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 26568 # Simulator instruction rate (inst/s)
-host_mem_usage 201268 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
-host_tick_rate 151609105 # Simulator tick rate (ticks/s)
+host_inst_rate 6063 # Simulator instruction rate (inst/s)
+host_mem_usage 203244 # Number of bytes of host memory used
+host_seconds 0.93 # Real time elapsed on the host
+host_tick_rate 34635885 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5656 # Number of instructions simulated
sim_seconds 0.000032 # Number of seconds simulated
@@ -218,24 +218,6 @@ system.cpu.not_idle_fraction 1 # Pe
system.cpu.numCycles 64644 # number of cpu cycles simulated
system.cpu.num_insts 5656 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_misses 0 # DTB write misses
-system.cpu.tlb.write_misses 0 # DTB write misses
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 970388ae5..ade758841 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
size=64
[system.cpu.itb]
-type=SparcITB
+type=SparcTLB
size=64
[system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index eefaf1737..c66e3090a 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:17:34
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py quick/00.hello/sparc/linux/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:32:53
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 2701000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index b09b910ba..90590228c 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 25851 # Simulator instruction rate (inst/s)
-host_mem_usage 193720 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
-host_tick_rate 13060676 # Simulator tick rate (ticks/s)
+host_inst_rate 179147 # Simulator instruction rate (inst/s)
+host_mem_usage 195464 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 89901478 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index f68b9582f..2bb5be9ae 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=SparcITB
+type=SparcTLB
size=64
[system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index fcae28521..b434e54e7 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:17:34
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py quick/00.hello/sparc/linux/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:32
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 29031000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index cf7518d98..011b7eb96 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 21374 # Simulator instruction rate (inst/s)
-host_mem_usage 201092 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
-host_tick_rate 116036277 # Simulator tick rate (ticks/s)
+host_inst_rate 18112 # Simulator instruction rate (inst/s)
+host_mem_usage 202936 # Number of bytes of host memory used
+host_seconds 0.30 # Real time elapsed on the host
+host_tick_rate 98375821 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index 1a9a034e8..911046b97 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=X86DTB
+type=X86TLB
size=64
[system.cpu.itb]
-type=X86ITB
+type=X86TLB
size=64
[system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 60f35ee0f..4e7b9509a 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:59:09
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:59:49
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 454f55a63..e01f452d4 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 165270 # Simulator instruction rate (inst/s)
-host_mem_usage 192880 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 95268287 # Simulator tick rate (ticks/s)
+host_inst_rate 250793 # Simulator instruction rate (inst/s)
+host_mem_usage 195416 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 144131714 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index d1edd6c59..ff74f91e4 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=X86DTB
+type=X86TLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=X86ITB
+type=X86TLB
size=64
[system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index a84f40e19..dbbe5f90a 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:37:33
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 13:09:24
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index b8a17302a..dd6fe41f9 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 139542 # Simulator instruction rate (inst/s)
-host_mem_usage 200396 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 436046426 # Simulator tick rate (ticks/s)
+host_inst_rate 171022 # Simulator instruction rate (inst/s)
+host_mem_usage 202960 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 533375213 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000030 # Number of seconds simulated