diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
| commit | 5d5b0f49cc125973fb7048ad86bf85ab5ed57772 (patch) | |
| tree | 0840a5055d8d8103eb22bcbe1ad90498e3db8aee /tests/quick/00.hello | |
| parent | d0b0a555151232566550c837f9d4d061bf3d4686 (diff) | |
| download | gem5-5d5b0f49cc125973fb7048ad86bf85ab5ed57772.tar.xz | |
Stats: Update stats for minor O3 changes below.
Diffstat (limited to 'tests/quick/00.hello')
4 files changed, 885 insertions, 883 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 811dc859b..7a48bdd9d 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -7,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 4 2011 13:56:47 -M5 started May 4 2011 14:21:49 -M5 executing on nadc-0364 +M5 compiled May 16 2011 15:11:25 +M5 started May 16 2011 15:11:56 +M5 executing on nadc-0271 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10782500 because target called exit() +Exiting @ tick 10758500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 7db13d16a..b65280987 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,514 +1,514 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 97592 # Simulator instruction rate (inst/s) -host_mem_usage 257968 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 182664453 # Simulator tick rate (ticks/s) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 10758500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 88454 # Simulator instruction rate (inst/s) +host_tick_rate 165780634 # Simulator tick rate (ticks/s) +host_mem_usage 251164 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10782500 # Number of ticks simulated +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.numCycles 21518 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 2191 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1669 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 732 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 725 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1851 # Number of BTB lookups +system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2185 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 238 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted -system.cpu.commit.branches 945 # Number of branches committed -system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.fetch.icacheStallCycles 1618 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11168 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2191 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 974 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2422 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.190999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.598414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9243 79.24% 79.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.94% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 153 1.31% 82.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 215 1.84% 84.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 195 1.67% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 261 2.24% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 124 1.06% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 97 0.83% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1151 9.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.101822 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.519007 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7384 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1181 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2267 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 786 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 350 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12143 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 786 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7644 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2054 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 189 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11385 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11181 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51381 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5492 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 15 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 493 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2353 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10217 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8487 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3978 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 11076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 11665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.727561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.389080 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8112 69.54% 69.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1403 12.03% 81.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 820 7.03% 88.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 520 4.46% 93.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 393 3.37% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 236 2.02% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 143 1.23% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11665 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 6.01% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 116 63.39% 69.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56 30.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5246 61.81% 61.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2078 24.48% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1154 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 8487 # Type of FU issued +system.cpu.iq.rate 0.394414 # Inst issue rate +system.cpu.iq.fu_busy_cnt 183 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021562 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28807 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14215 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7753 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8650 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 786 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10244 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 136 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2353 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8154 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 333 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 3 # number of nop insts executed +system.cpu.iew.exec_refs 3053 # number of memory reference insts executed +system.cpu.iew.exec_branches 1361 # Number of branches executed +system.cpu.iew.exec_stores 1121 # Number of stores executed +system.cpu.iew.exec_rate 0.378939 # Inst execution rate +system.cpu.iew.wb_sent 7896 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7769 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3570 # num instructions producing a value +system.cpu.iew.wb_consumers 7022 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.361047 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.508402 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 4400 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4364 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 10921 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525501 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286416 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 334 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.527482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.289859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8444 77.32% 77.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1188 10.88% 88.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 479 4.39% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 318 2.91% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 171 1.57% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 152 1.39% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 62 0.57% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.30% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8406 77.26% 77.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1187 10.91% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 477 4.38% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 317 2.91% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.56% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 153 1.41% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 62 0.57% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 34 0.31% 99.32% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 74 0.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10921 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10880 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 2139 # Number of memory references committed system.cpu.commit.loads 1201 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.refs 2139 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 20788 # The number of ROB reads +system.cpu.rob.rob_writes 21080 # The number of ROB writes +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9853 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.757798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.757798 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 1795 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 32493.670886 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29240.566038 # average ReadReq mshr miss latency +system.cpu.cpi 3.749434 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.749434 # CPI: Total CPI of All Threads +system.cpu.ipc 0.266707 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.266707 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 37248 # number of integer regfile reads +system.cpu.int_regfile_writes 7653 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.misc_regfile_reads 13970 # number of misc regfile reads +system.cpu.misc_regfile_writes 24 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 146.709916 # Cycle average of tags in use +system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 285 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.519298 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 146.709916 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.071636 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits +system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1288 # number of overall hits +system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses +system.cpu.icache.demand_misses 330 # number of demand (read+write) misses +system.cpu.icache.overall_misses 330 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 11562500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 11562500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 11562500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1618 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1618 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1618 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.203956 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.203956 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.203956 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35037.878788 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35037.878788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35037.878788 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 9568500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9568500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9568500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.176143 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.176143 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.176143 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33573.684211 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 89.574063 # Cycle average of tags in use +system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.295302 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 89.574063 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021869 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1637 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5134000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.088022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 158 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059053 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 106 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2259 # number of overall hits +system.cpu.dcache.ReadReq_misses 159 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 450 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 450 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10420500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 15553000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 15553000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1796 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35800.687285 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35880.952381 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10418000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.088530 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1507000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 15.398649 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.166113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.166113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32279.874214 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35809.278351 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34562.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34562.222222 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2708 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34636.971047 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31125 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15552000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.165805 # miss rate for demand accesses -system.cpu.dcache.demand_misses 449 # number of demand (read+write) misses +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4606500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.054653 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 89.451060 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021839 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2708 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34636.971047 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31125 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2259 # number of overall hits -system.cpu.dcache.overall_miss_latency 15552000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.165805 # miss rate for overall accesses -system.cpu.dcache.overall_misses 449 # number of overall misses system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4606500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.054653 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_misses 107 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1507500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4607000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4607000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.059577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.055002 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.055002 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28967.289720 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35892.857143 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 89.451060 # Cycle average of tags in use -system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 1179 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 352 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 12101 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 7437 # Number of cycles decode is idle -system.cpu.decode.RunCycles 2257 # Number of cycles decode is running -system.cpu.decode.SquashCycles 777 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 565 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2185 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1628 # Number of cache lines fetched -system.cpu.fetch.Cycles 2410 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11189 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.101317 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1628 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 963 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.518826 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.186202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.597096 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9287 79.40% 79.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223 1.91% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 1.27% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 211 1.80% 84.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 194 1.66% 86.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 259 2.21% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 122 1.04% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 98 0.84% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1154 9.87% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11697 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35051.051051 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33594.076655 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1295 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 11672000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.204545 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 333 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9641500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.176290 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 287 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.512195 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1628 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35051.051051 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33594.076655 # average overall mshr miss latency -system.cpu.icache.demand_hits 1295 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 11672000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.204545 # miss rate for demand accesses -system.cpu.icache.demand_misses 333 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9641500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.176290 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 287 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 147.191898 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.071871 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1628 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35051.051051 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33594.076655 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1295 # number of overall hits -system.cpu.icache.overall_miss_latency 11672000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.204545 # miss rate for overall accesses -system.cpu.icache.overall_misses 333 # number of overall misses -system.cpu.icache.overall_mshr_hits 46 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9641500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.176290 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 287 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.sampled_refs 287 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 147.191898 # Cycle average of tags in use -system.cpu.icache.total_refs 1295 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 9869 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 1360 # Number of branches executed -system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_rate 0.377446 # Inst execution rate -system.cpu.iew.exec_refs 3052 # number of memory reference insts executed -system.cpu.iew.exec_stores 1120 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2335 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10208 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8140 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 777 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 1134 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 6995 # num instructions consuming a value -system.cpu.iew.wb_count 7761 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.509078 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 3561 # num instructions producing a value -system.cpu.iew.wb_rate 0.359872 # insts written-back per cycle -system.cpu.iew.wb_sent 7887 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 37201 # number of integer regfile reads -system.cpu.int_regfile_writes 7643 # number of integer regfile writes -system.cpu.ipc 0.266113 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.266113 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5232 61.80% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2072 24.47% 86.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1153 13.62% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8466 # Type of FU issued -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 182 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021498 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.04% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 115 63.19% 69.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56 30.77% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 8628 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 28796 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7745 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 14142 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 10181 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8466 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3941 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedOperandsExamined 10938 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 11697 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.723775 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.386140 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8148 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1408 12.04% 81.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 816 6.98% 88.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 516 4.41% 93.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 394 3.37% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 234 2.00% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 143 1.22% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11697 # Number of insts issued each cycle -system.cpu.iq.rate 0.392562 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 185.420659 # Cycle average of tags in use +system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 347 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.112392 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 185.420659 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005659 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 39 # number of ReadReq hits +system.cpu.l2cache.demand_hits 39 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 39 # number of overall hits +system.cpu.l2cache.ReadReq_misses 353 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 395 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 395 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 12138500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1447000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 13585500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 13585500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1446500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.900510 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 393 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34391.549296 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31237.822350 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 38 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12209000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.903308 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 355 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 10902000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.888041 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 349 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.108883 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.910138 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.910138 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34386.685552 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34452.380952 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34393.670886 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34393.670886 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34396.725441 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.524297 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 38 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13655500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.912644 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 397 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12217000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.898851 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 185.920349 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005674 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34396.725441 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.524297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 38 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13655500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.912644 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 397 # number of overall misses system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12217000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.898851 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 347 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 349 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 10837500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 12152500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 12152500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.896313 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.896313 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31231.988473 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 185.920349 # Cycle average of tags in use -system.cpu.l2cache.total_refs 38 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2335 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 13994 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.numCycles 21566 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 7695 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 122 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 51738 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 11352 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 11162 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 2047 # Number of cycles rename is running -system.cpu.rename.SquashCycles 777 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 186 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 5473 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 51218 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 15 # count of serializing insts renamed -system.cpu.rename.skidInsts 482 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 20793 # The number of ROB reads -system.cpu.rob.rob_writes 20998 # The number of ROB writes -system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index f23e1efe6..a4e55b227 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 13:30:37 -M5 started Apr 21 2011 14:05:23 -M5 executing on maize +M5 compiled May 17 2011 12:22:59 +M5 started May 17 2011 13:06:27 +M5 executing on nadc-0309 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11371000 because target called exit() +Exiting @ tick 11369000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 71886c36a..fb3f0ce4d 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,303 +1,106 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 99680 # Simulator instruction rate (inst/s) -host_mem_usage 212240 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 115331857 # Simulator tick rate (ticks/s) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11369000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 133340 # Simulator instruction rate (inst/s) +host_tick_rate 154514196 # Simulator tick rate (ticks/s) +host_mem_usage 245132 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11371000 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 931 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 2531 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 22739 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 2757 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2757 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 2758 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2758 # Number of BP lookups +system.cpu.BPredUnit.BTBLookups 2530 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 929 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted -system.cpu.commit.branches 1214 # Number of branches committed -system.cpu.commit.bw_lim_events 141 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9222 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 11809 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.830638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.597584 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8189 69.35% 69.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1225 10.37% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 582 4.93% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11809 # Number of insts commited each cycle -system.cpu.commit.count 9809 # Number of instructions committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.int_insts 9714 # Number of committed integer instructions. -system.cpu.commit.loads 1056 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 1990 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 9809 # Number of Instructions Simulated -system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.318585 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.318585 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses -system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 85.873455 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020965 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2039 # number of overall hits -system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses -system.cpu.dcache.overall_misses 426 # number of overall misses -system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 85.873455 # Cycle average of tags in use -system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 1369 # Number of cycles decode is blocked -system.cpu.decode.DecodedInsts 22088 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 7085 # Number of cycles decode is idle -system.cpu.decode.RunCycles 3278 # Number of cycles decode is running -system.cpu.decode.SquashCycles 1477 # Number of cycles decode is squashing -system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2758 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1703 # Number of cache lines fetched -system.cpu.fetch.Cycles 3590 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 238 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12847 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1700 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12836 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2757 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3597 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.121268 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1703 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 931 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.564877 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.734834 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.110520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1700 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.109101 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9786 73.66% 73.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 161 1.21% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 122 0.92% 75.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.71% 77.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 192 1.45% 78.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 168 1.26% 80.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 1.93% 82.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 171 1.29% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2202 16.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9775 73.60% 73.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 168 1.26% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 126 0.95% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.70% 77.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 192 1.45% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 1.26% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 259 1.95% 82.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 168 1.26% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2200 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13286 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1703 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36577.562327 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1342 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13204500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.211979 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10354500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.173224 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.549153 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1703 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36577.562327 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35100 # average overall mshr miss latency -system.cpu.icache.demand_hits 1342 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13204500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.211979 # miss rate for demand accesses -system.cpu.icache.demand_misses 361 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10354500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.173224 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 144.881554 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.070743 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1703 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36577.562327 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35100 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1342 # number of overall hits -system.cpu.icache.overall_miss_latency 13204500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.211979 # miss rate for overall accesses -system.cpu.icache.overall_misses 361 # number of overall misses -system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10354500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.173224 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 144.881554 # Cycle average of tags in use -system.cpu.icache.total_refs 1342 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 566 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 1545 # Number of branches executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_rate 0.675461 # Inst execution rate -system.cpu.iew.exec_refs 2952 # number of memory reference insts executed -system.cpu.iew.exec_stores 1295 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2082 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1617 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19032 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 693 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15362 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1477 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 1026 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 683 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 497 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 14668 # num instructions consuming a value -system.cpu.iew.wb_count 15056 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.677734 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 9941 # num instructions producing a value -system.cpu.iew.wb_rate 0.662006 # insts written-back per cycle -system.cpu.iew.wb_sent 15179 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 22959 # number of integer regfile reads -system.cpu.int_regfile_writes 13993 # number of integer regfile writes -system.cpu.ipc 0.431298 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.431298 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 12893 80.31% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16055 # Type of FU issued -system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009156 # FU busy rate (busy events/executed inst) +system.cpu.fetch.rateDist::total 13282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121245 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.564493 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7076 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1369 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3285 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1475 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 22079 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1475 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7317 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 565 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 440 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3105 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 380 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 21002 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 52 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 248 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 19737 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 44285 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 44269 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 10369 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1483 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2081 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1618 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 18991 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 16049 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8597 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10847 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13282 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.208327 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.917321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8198 61.72% 61.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1295 9.75% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 980 7.38% 78.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 727 5.47% 84.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 779 5.87% 90.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 582 4.38% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13282 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 101 68.71% 68.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 68.71% # attempts to use FU when none available @@ -332,129 +135,326 @@ system.cpu.iq.fu_full::MemRead 27 18.37% 87.07% # at system.cpu.iq.fu_full::MemWrite 19 12.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 16193 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 45588 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 15052 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 27650 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 18999 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16055 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8610 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 10851 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 13286 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.208415 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.917020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8201 61.73% 61.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1290 9.71% 71.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 986 7.42% 78.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 726 5.46% 84.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 782 5.89% 90.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 580 4.37% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13286 # Number of insts issued each cycle -system.cpu.iq.rate 0.705931 # Inst issue rate -system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34603.896104 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2664500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 12887 80.30% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 16049 # Type of FU issued +system.cpu.iq.rate 0.705792 # Inst issue rate +system.cpu.iq.fu_busy_cnt 147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009159 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 45572 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 27629 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15050 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 16187 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1025 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1475 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 19024 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 215 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2081 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1618 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 498 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 15360 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 689 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 2952 # number of memory reference insts executed +system.cpu.iew.exec_branches 1546 # Number of branches executed +system.cpu.iew.exec_stores 1295 # Number of stores executed +system.cpu.iew.exec_rate 0.675491 # Inst execution rate +system.cpu.iew.wb_sent 15177 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15054 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9950 # num instructions producing a value +system.cpu.iew.wb_consumers 14675 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.662034 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.678024 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11807 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.830778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.597683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8187 69.34% 69.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1225 10.38% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 582 4.93% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11807 # Number of insts commited each cycle +system.cpu.commit.count 9809 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 1990 # Number of memory references committed +system.cpu.commit.loads 1056 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 1214 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 9714 # Number of committed integer instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.bw_lim_events 141 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 30689 # The number of ROB reads +system.cpu.rob.rob_writes 39546 # The number of ROB writes +system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 9809 # Number of Instructions Simulated +system.cpu.committedInsts_total 9809 # Number of Instructions Simulated +system.cpu.cpi 2.318177 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.318177 # CPI: Total CPI of All Threads +system.cpu.ipc 0.431373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.431373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 22959 # number of integer regfile reads +system.cpu.int_regfile_writes 13989 # number of integer regfile writes +system.cpu.fp_regfile_reads 4 # number of floating regfile reads +system.cpu.misc_regfile_reads 6812 # number of misc regfile reads +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 144.881621 # Cycle average of tags in use +system.cpu.icache.total_refs 1339 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.538983 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 144.881621 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.070743 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1339 # number of ReadReq hits +system.cpu.icache.demand_hits 1339 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1339 # number of overall hits +system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses +system.cpu.icache.demand_misses 361 # number of demand (read+write) misses +system.cpu.icache.overall_misses 361 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 13205500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 13205500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 13205500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1700 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1700 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.212353 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.212353 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.212353 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36580.332410 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36580.332410 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36580.332410 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 10355500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10355500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10355500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.173529 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.173529 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.173529 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35103.389831 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 85.872025 # Cycle average of tags in use +system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 85.872025 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.020965 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits +system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2039 # number of overall hits +system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses +system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 426 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 178.189347 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 178.189347 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005438 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 437 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 12329000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2664000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 14993000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14993000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34244.444444 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12328000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34247.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34597.402597 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34308.924485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34308.924485 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34307.780320 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14992500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 13592000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 178.188786 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005438 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34307.780320 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14992500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 437 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 178.188786 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2082 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1617 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 6812 # number of misc regfile reads -system.cpu.numCycles 22743 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 565 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 52 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 7327 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 248 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 44292 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 21008 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 19746 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 3097 # Number of cycles rename is running -system.cpu.rename.SquashCycles 1477 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 380 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 10378 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 44276 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 440 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.skidInsts 1483 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 30699 # The number of ROB reads -system.cpu.rob.rob_writes 39564 # The number of ROB writes -system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |