diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
| commit | b85690e239616b703881b7734b0559f61f9eb75e (patch) | |
| tree | f144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/quick/00.hello | |
| parent | c30e615689148c6e5ecd06e86069cba716dec5e0 (diff) | |
| download | gem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz | |
update all the regresstion tests for release
--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/quick/00.hello')
41 files changed, 789 insertions, 792 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 2a139492e..882c78529 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 8155faf63..701034053 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 86aa4129f..c07021f5a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 606 # Number of BTB hits -global.BPredUnit.BTBLookups 1858 # Number of BTB lookups -global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted -global.BPredUnit.lookups 2195 # Number of BP lookups -global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -host_inst_rate 22780 # Simulator instruction rate (inst/s) +global.BPredUnit.BTBHits 524 # Number of BTB hits +global.BPredUnit.BTBLookups 1590 # Number of BTB lookups +global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted +global.BPredUnit.lookups 1843 # Number of BP lookups +global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target. +host_inst_rate 54565 # Simulator instruction rate (inst/s) host_mem_usage 154084 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host -host_tick_rate 14337041 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 44392410 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 127 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 3543500 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4588000 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6315 +system.cpu.commit.COM:committed_per_cycle.samples 8514 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4255 6737.93% - 1 915 1448.93% - 2 408 646.08% - 3 162 256.53% - 4 140 221.69% - 5 91 144.10% - 6 121 191.61% - 7 102 161.52% - 8 121 191.61% + 0 6195 7276.25% + 1 1158 1360.11% + 2 469 550.86% + 3 176 206.72% + 4 131 153.86% + 5 99 116.28% + 6 109 128.02% + 7 73 85.74% + 8 104 122.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses -system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses +system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1857 # number of overall hits -system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses -system.cpu.dcache.overall_misses 471 # number of overall misses -system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1811 # number of overall hits +system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses +system.cpu.dcache.overall_misses 476 # number of overall misses +system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use -system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use +system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched -system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched +system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 7088 +system.cpu.fetch.rateDist.samples 9197 system.cpu.fetch.rateDist.min_value 0 - 0 4755 6708.52% - 1 197 277.93% - 2 177 249.72% - 3 163 229.97% - 4 234 330.14% - 5 170 239.84% - 6 198 279.35% - 7 114 160.84% - 8 1080 1523.70% + 0 7219 7849.30% + 1 167 181.58% + 2 147 159.83% + 3 129 140.26% + 4 200 217.46% + 5 139 151.14% + 6 181 196.80% + 7 99 107.64% + 8 916 995.98% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency -system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses -system.cpu.icache.demand_misses 328 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency +system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses +system.cpu.icache.demand_misses 330 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1288 # number of overall hits -system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses -system.cpu.icache.overall_misses 328 # number of overall misses -system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses +system.cpu.icache.overall_hits 1141 # number of overall hits +system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses +system.cpu.icache.overall_misses 330 # number of overall misses +system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use -system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use +system.cpu.icache.total_refs 1141 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1203 # Number of branches executed -system.cpu.iew.EXEC:nop 41 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate -system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1148 # Number of branches executed +system.cpu.iew.EXEC:nop 40 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate +system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 977 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5598 # num instructions consuming a value -system.cpu.iew.WB:count 7767 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back +system.cpu.iew.WB:consumers 5205 # num instructions consuming a value +system.cpu.iew.WB:count 7402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4153 # num instructions producing a value -system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle -system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions +system.cpu.iew.WB:producers 3866 # num instructions producing a value +system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle +system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5713 66.97% # Type of FU issued + (null) 2 0.03% # Type of FU issued + IntAlu 5322 66.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued + FloatAdd 2 0.03% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1773 20.78% # Type of FU issued - MemWrite 1040 12.19% # Type of FU issued + MemRead 1662 20.82% # Type of FU issued + MemWrite 992 12.43% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 7 5.47% # attempts to use FU when none available + IntAlu 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 78 60.94% # attempts to use FU when none available - MemWrite 43 33.59% # attempts to use FU when none available + MemRead 71 66.98% # attempts to use FU when none available + MemWrite 35 33.02% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9197 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4068 5739.28% - 1 771 1087.75% - 2 763 1076.47% - 3 485 684.26% - 4 504 711.06% - 5 295 416.20% - 6 144 203.16% - 7 40 56.43% - 8 18 25.40% + 0 5952 6471.68% + 1 1107 1203.65% + 2 919 999.24% + 3 442 480.59% + 4 375 407.74% + 5 250 271.83% + 6 115 125.04% + 7 26 28.27% + 8 11 11.96% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate -system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.overall_misses 483 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,28 +380,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 7088 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking +system.cpu.numCycles 9197 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index eeba3846f..3ab3ef422 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:06 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:39 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 3543500 because target called exit() +Exiting @ tick 4588000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 26009ca4f..bf00075ce 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index f8e40871a..117159126 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 0f64469e9..4e1bd9447 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 357156 # Simulator instruction rate (inst/s) -host_mem_usage 148180 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 171417285 # Simulator tick rate (ticks/s) +host_inst_rate 576538 # Simulator instruction rate (inst/s) +host_mem_usage 148208 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 276546720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 5acc408a3..6848303a8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:08 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 025531062..6daf0bd85 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index fa1054e9e..7041702bf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index afdac247d..ad908bf47 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 215467 # Simulator instruction rate (inst/s) -host_mem_usage 153656 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 193088667 # Simulator tick rate (ticks/s) +host_inst_rate 280990 # Simulator instruction rate (inst/s) +host_mem_usage 153668 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 642654954 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5135000 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13168000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1288000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1196000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1022000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 949000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2310000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2145000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2310000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2145000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.640117 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13960.288809 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3867000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3590000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3867000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3590000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3867000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3590000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.241810 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4851000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5733000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5733000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 232.802947 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5135000 # number of cpu cycles simulated +system.cpu.numCycles 13168000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index a79e87c66..3fc11f801 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:09 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5135000 because target called exit() +Exiting @ tick 13168000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 1e3b2746e..40a8f1a84 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 5df02e4ff..46dc2c36a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index d3074bcf9..c1b1b7625 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 162 # Number of BTB hits -global.BPredUnit.BTBLookups 671 # Number of BTB lookups -global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 427 # Number of conditional branches predicted -global.BPredUnit.lookups 860 # Number of BP lookups -global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -host_inst_rate 31252 # Simulator instruction rate (inst/s) +global.BPredUnit.BTBHits 132 # Number of BTB hits +global.BPredUnit.BTBLookups 584 # Number of BTB lookups +global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 376 # Number of conditional branches predicted +global.BPredUnit.lookups 738 # Number of BP lookups +global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target. +host_inst_rate 54176 # Simulator instruction rate (inst/s) host_mem_usage 153592 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 21107113 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 46286693 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1619000 # Number of ticks simulated +sim_ticks 2053000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 2977 +system.cpu.commit.COM:committed_per_cycle.samples 3906 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 2102 7060.80% - 1 212 712.13% - 2 297 997.65% - 3 114 382.94% - 4 83 278.80% - 5 58 194.83% - 6 30 100.77% - 7 22 73.90% - 8 59 198.19% + 0 2949 7549.92% + 1 266 681.00% + 2 333 852.53% + 3 131 335.38% + 4 74 189.45% + 5 64 163.85% + 6 29 74.24% + 7 19 48.64% + 8 41 104.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.cpi 1.721408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.721408 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5456.521739 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4737.288136 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses -system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses +system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 405000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 687 # number of overall hits -system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses -system.cpu.dcache.overall_misses 144 # number of overall misses -system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses +system.cpu.dcache.overall_hits 668 # number of overall hits +system.cpu.dcache.overall_miss_latency 779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses +system.cpu.dcache.overall_misses 140 # number of overall misses +system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 405000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,90 +119,89 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use -system.cpu.dcache.total_refs 687 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 51.851940 # Cycle average of tags in use +system.cpu.dcache.total_refs 668 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 860 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 736 # Number of cache lines fetched -system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 767 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.fetch.Branches 738 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 654 # Number of cache lines fetched +system.cpu.fetch.Cycles 1440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.179606 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.140180 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 3239 +system.cpu.fetch.rateDist.samples 4109 system.cpu.fetch.rateDist.min_value 0 - 0 2309 7128.74% - 1 47 145.11% - 2 82 253.16% - 3 70 216.12% - 4 128 395.18% - 5 58 179.07% - 6 37 114.23% - 7 46 142.02% - 8 462 1426.37% + 0 3325 8091.99% + 1 32 77.88% + 2 74 180.09% + 3 53 128.99% + 4 99 240.93% + 5 49 119.25% + 6 38 92.48% + 7 35 85.18% + 8 404 983.21% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5296.019900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4553.763441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 847000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency -system.cpu.icache.demand_hits 543 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses -system.cpu.icache.demand_misses 193 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency +system.cpu.icache.demand_hits 453 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses +system.cpu.icache.demand_misses 201 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 847000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency +system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 543 # number of overall hits -system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses -system.cpu.icache.overall_misses 193 # number of overall misses -system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 453 # number of overall hits +system.cpu.icache.overall_miss_latency 1064500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses +system.cpu.icache.overall_misses 201 # number of overall misses +system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 847000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -218,58 +217,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use -system.cpu.icache.total_refs 543 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 106.237740 # Cycle average of tags in use +system.cpu.icache.total_refs 453 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 535 # Number of branches executed -system.cpu.iew.EXEC:nop 256 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate -system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 339 # Number of stores executed +system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 501 # Number of branches executed +system.cpu.iew.EXEC:nop 234 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.727184 # Inst execution rate +system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 333 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1857 # num instructions consuming a value -system.cpu.iew.WB:count 3126 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back +system.cpu.iew.WB:consumers 1652 # num instructions consuming a value +system.cpu.iew.WB:count 2914 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1462 # num instructions producing a value -system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle -system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1321 # num instructions producing a value +system.cpu.iew.WB:rate 0.709175 # insts written-back per cycle +system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued +system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.580920 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2413 71.45% # Type of FU issued + IntAlu 2178 70.83% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 617 18.27% # Type of FU issued - MemWrite 346 10.25% # Type of FU issued + MemRead 561 18.24% # Type of FU issued + MemWrite 335 10.89% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 2.70% # attempts to use FU when none available + IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +296,42 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 14 37.84% # attempts to use FU when none available - MemWrite 22 59.46% # attempts to use FU when none available + MemRead 12 34.29% # attempts to use FU when none available + MemWrite 21 60.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 3239 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4109 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2006 6193.27% - 1 362 1117.63% - 2 258 796.54% - 3 236 728.62% - 4 193 595.86% - 5 111 342.70% - 6 53 163.63% - 7 14 43.22% - 8 6 18.52% + 0 2849 6933.56% + 1 475 1156.00% + 2 270 657.09% + 3 217 528.11% + 4 159 386.96% + 5 86 209.30% + 6 34 82.75% + 7 13 31.64% + 8 6 14.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate -system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.748357 # Inst issue rate +system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4522.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1221000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +340,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1221000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1221000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 271 # number of overall misses +system.cpu.l2cache.overall_misses 270 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,27 +378,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 158.236294 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 3239 # number of cpu cycles simulated +system.cpu.numCycles 4109 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 696 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed +system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index e582c15a8..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 835f03aa2..587034bb2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:41 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1619000 because target called exit() +Exiting @ tick 2053000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 3e6a662e6..20dfddd0a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index a2be80e9b..acc734991 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 16257c237..e82d837af 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254768 # Simulator instruction rate (inst/s) -host_mem_usage 147764 # Number of bytes of host memory used +host_inst_rate 484860 # Simulator instruction rate (inst/s) +host_mem_usage 147796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 121316260 # Simulator tick rate (ticks/s) +host_tick_rate 225459318 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index ddbbe3d32..3b5348194 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 52183bdb1..1c1daa355 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 05d289a63..45a8521ac 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 8671d784f..756244d02 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 125225 # Simulator instruction rate (inst/s) +host_inst_rate 228404 # Simulator instruction rate (inst/s) host_mem_usage 153176 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 116347710 # Simulator tick rate (ticks/s) +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 552831639 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2444000 # Number of ticks simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6472000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3890.909091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2890.909091 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3722.222222 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 100500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 73500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 314500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 232500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 314500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 232500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 51.430454 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3733.128834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2733.128834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 608500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 445500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 608500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 445500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 608500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 445500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 89.421061 # Cycle average of tags in use +system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2767.346939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1766.346939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 678000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 432755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 432755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 432755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 140.951761 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2444000 # number of cpu cycles simulated +system.cpu.numCycles 6472000 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index d2bc8bfb7..f5e3a6008 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2444000 because target called exit() +Exiting @ tick 6472000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 80ef56747..ea3ba751b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 9f8b84468..06a3d271d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index daf99515d..6a0c251b5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 7127 # Simulator instruction rate (inst/s) -host_mem_usage 148488 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 3561193 # Simulator tick rate (ticks/s) +host_inst_rate 535701 # Simulator instruction rate (inst/s) +host_mem_usage 148368 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 257653061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index b975f8f18..7fb23e5a5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:35 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 29fcae5de..a5d4e6583 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index d5d160f1e..3f8a51cf4 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 71b0896dd..41bb7c8b7 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 224031 # Simulator instruction rate (inst/s) -host_mem_usage 153864 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 205051803 # Simulator tick rate (ticks/s) +host_inst_rate 273338 # Simulator instruction rate (inst/s) +host_mem_usage 153844 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 633390216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5264500 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13362000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3762.195122 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2762.195122 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 308500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1148000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1066000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 184500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 134500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 650000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 493000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1848000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 361000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1716000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits -system.cpu.dcache.overall_miss_latency 493000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1848000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 361000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1716000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 86.050916 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 85.283494 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3740.924092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2740.924092 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13986.798680 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1133500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4238000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3935000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1133500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4238000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3935000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 1133500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4238000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 830500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3935000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 137.160443 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.309471 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2743.648961 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1742.648961 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1188000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5629000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754567 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4763000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1188000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5629000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754567 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1188000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5629000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754567 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 224.535228 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.872415 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5264500 # number of cpu cycles simulated +system.cpu.numCycles 13362000 # number of cpu cycles simulated system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 1cc143ec3..6b688641a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:36 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5264500 because target called exit() +Exiting @ tick 13362000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 5d4dafee7..0e142e6ce 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index 1a521c678..1666790d0 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index bbc3d0e4f..8e0baaf8b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 16183 # Simulator instruction rate (inst/s) -host_mem_usage 149132 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 8071210 # Simulator tick rate (ticks/s) +host_inst_rate 439375 # Simulator instruction rate (inst/s) +host_mem_usage 149124 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 211870315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 84e837005..9e1770f92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:04 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2431000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 4371849c9..fdb2bc3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out index b02683337..89910d3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index c6b55a6f2..839307810 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 189060 # Simulator instruction rate (inst/s) -host_mem_usage 154496 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 164285984 # Simulator tick rate (ticks/s) +host_inst_rate 239687 # Simulator instruction rate (inst/s) +host_mem_usage 154512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 542234464 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 4347500 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11221000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3740.740741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2740.740741 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13796.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12796.296296 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 202000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 745000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 148000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 691000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 304500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1176000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 220500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1092000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 506500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1921000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 368500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1783000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits -system.cpu.dcache.overall_miss_latency 506500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1921000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 368500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1783000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.314216 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.705022 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3796.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2796.875000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13914.062500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12914.062500 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 972000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3562000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 716000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3306000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 972000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3562000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 716000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3306000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits -system.cpu.icache.overall_miss_latency 972000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3562000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 716000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3306000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.238100 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.172725 # Cycle average of tags in use system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2760.869565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1759.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5083000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 688109 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4301000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5083000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 688109 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5083000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 688109 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 197.030867 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.304892 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4347500 # number of cpu cycles simulated +system.cpu.numCycles 11221000 # number of cpu cycles simulated system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 6a58f8e2a..65bf4abca 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4347500 because target called exit() +Exiting @ tick 11221000 because target called exit() |