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author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
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committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
commit | 005892719047c3b4b383d9aeeeb481039518f661 (patch) | |
tree | b2d967a9ffea13f73e092804ae141d9520ff109c /tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing | |
parent | 2a3cefe15115a094eadd74a659a2f919a83ac6a4 (diff) | |
download | gem5-005892719047c3b4b383d9aeeeb481039518f661.tar.xz |
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing')
0 files changed, 0 insertions, 0 deletions