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| author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
| commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
| tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing | |
| parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
| download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz | |
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing')
3 files changed, 34 insertions, 18 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 9c8da927d..fa7d3cfec 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu.fuPool] @@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu.l2cache] diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 7101807df..46bfe60b8 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 6 2009 18:15:46 -M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip -M5 started Mar 6 2009 18:23:16 +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:44:23 M5 executing on maize -command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 783867939..ae5c73ad7 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106034 # Simulator instruction rate (inst/s) -host_mem_usage 203088 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 118060043 # Simulator tick rate (ticks/s) +host_inst_rate 98882 # Simulator instruction rate (inst/s) +host_mem_usage 203072 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 110106309 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -211,10 +211,14 @@ system.cpu.decode.DECODE:RunCycles 4878 # Nu system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 6300 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 6155 # DTB hits -system.cpu.dtb.misses 145 # DTB misses +system.cpu.dtb.data_accesses 6300 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 6155 # DTB hits +system.cpu.dtb.data_misses 145 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 4144 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 4056 # DTB read hits @@ -551,10 +555,22 @@ system.cpu.iq.iqSquashedInstsExamined 9662 # Nu system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 4162 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 4113 # ITB hits -system.cpu.itb.misses 49 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 4162 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 4113 # ITB hits +system.cpu.itb.fetch_misses 49 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency |